Mouna Baklouti

Orcid: 0000-0001-9862-8506

According to our database1, Mouna Baklouti authored at least 59 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Towards an Optimized Blockchain-Based Secure Medical Prescription-Management System.
Future Internet, July, 2024

An Optimized Effective Authentication Process for E-Health Application.
Int. J. Online Biomed. Eng., 2024

Design Space Exploration of HW Accelerators and Network Infrastructure for FPGA-Based MPSoC.
IEEE Access, 2024

ML-based failure detection approach for predictive maintenance in an industry 4.0 oriented web manufacturing control application.
Proceedings of the 7th IEEE International Conference on Advanced Technologies, 2024

2023
Energy-Aware IoT-Based Method for a Hybrid On-Wrist Fall Detection System Using a Supervised Dictionary Learning Technique.
Sensors, April, 2023

NFT-IoT Pharma Chain : IoT Drug traceability system based on Blockchain and Non Fungible Tokens (NFTs).
J. King Saud Univ. Comput. Inf. Sci., February, 2023

Breast Cancer Detection Based DenseNet with Attention Model in Mammogram Images.
Proceedings of the Model and Data Engineering - 12th International Conference, 2023

STM32 miner : A lightweight blockchain mining system.
Proceedings of the 2023 IEEE International Conference on Design, 2023

HealthBeat traceability platform based on blockchain technology.
Proceedings of the 2023 IEEE International Conference on Design, 2023

2022
LoRaChainCare: An IoT Architecture Integrating Blockchain and LoRa Network for Personal Health Care Data Monitoring.
Sensors, 2022

SIT: Stochastic Input Transformation to Defend Against Adversarial Attacks on Deep Neural Networks.
IEEE Des. Test, 2022

Defending with Errors: Approximate Computing for Robustness of Deep Neural Networks.
CoRR, 2022

Blockchain for IoT-Based Healthcare using secure and privacy-preserving watermark.
Proceedings of the 15th International Conference on Security of Information and Networks, 2022

Design of Multiprocessor Architecture for Watermarking and Tracing Images Using QR Code.
Proceedings of the Intelligent Decision Technologies, 2022

On-wrist Based Datasets Exploration for an IoT Wearable Fall Detection.
Proceedings of the Advances in Computational Collective Intelligence, 2022

2021
Semantic Representation Driven by a Musculoskeletal Ontology for Bone Tumors Diagnosis.
Proceedings of the Intelligent Systems Design and Applications, 2021

A Sparse Representation Classification for Noise Robust Wrist-based Fall Detection.
Proceedings of the 14th International Joint Conference on Biomedical Engineering Systems and Technologies, 2021

Defensive approximation: securing CNNs using approximate computing.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020
Defensive Approximation: Enhancing CNNs Security through Approximate Computing.
CoRR, 2020

Robust and Secure Watermarking Technique for E-Health Applications.
Proceedings of the 12th International Conference on Soft Computing and Pattern Recognition (SoCPaR 2020), 2020

A Novel On-Wrist Fall Detection System Using Supervised Dictionary Learning Technique.
Proceedings of the Impact of Digital Technologies on Public Health in Developed and Developing Countries, 2020

Embedded Landmark implementation for Deep Learning pre-processing.
Proceedings of the 5th International Conference on Advanced Technologies for Signal and Image Processing, 2020

2019
SCAC: Weakly-coupled execution model for massively parallel systems.
Microprocess. Microsystems, 2019

HEAP: A Heterogeneous Approximate Floating-Point Multiplier for Error Tolerant Applications.
Proceedings of the 30th International Workshop on Rapid System Prototyping, 2019

Testbed Implementation of a Fuzzy based Energy Efficient Clustering Algorithm for Wireless Sensor Networks.
Proceedings of the 16th International Multi-Conference on Systems, Signals & Devices, 2019

2018
Comparing Three Clustering-based Scheduling Methods for Energy-Aware Rapid Design of MP2SoCs.
J. Signal Process. Syst., 2018

HAPE: A high-level area-power estimation framework for FPGA-based accelerators.
Microprocess. Microsystems, 2018

2017
Hardware resource estimation for heterogeneous FPGA-based SoCs.
Proceedings of the Symposium on Applied Computing, 2017

A Rapid Data Communication Exploration Tool for Hybrid CPU-FPGA Architectures.
Proceedings of the 25th Euromicro International Conference on Parallel, 2017

Performance Exploration of AMBA AXI4 Bus Protocols for Wireless Sensor Networks.
Proceedings of the 14th IEEE/ACS International Conference on Computer Systems and Applications, 2017

2016
Off-Line DVFS Integration in MDE-Based Design Space Exploration Framework for MP2SoC Systems.
Proceedings of the 25th IEEE International Conference on Enabling Technologies: Infrastructure for Collaborative Enterprises, 2016

Development of a two-threshold-based fall detection algorithm for elderly health monitoring.
Proceedings of the Tenth IEEE International Conference on Research Challenges in Information Science, 2016

SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

On Exploiting Energy-Aware Scheduling Algorithms for MDE-Based Design Space Exploration of MP2SoC.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

A comparison and performance evaluation of FPGA soft-cores for embedded multi-core systems.
Proceedings of the 11th International Design & Test Symposium, 2016

Vivado HLS-based implementation of a fall detection decision core on an FPGA platform.
Proceedings of the 11th International Design & Test Symposium, 2016

Design and implementation of a fall detection system on a Zynq board.
Proceedings of the 13th IEEE/ACS International Conference of Computer Systems and Applications, 2016

2015
Hardware resource utilization optimization in FPGA-based Heterogeneous MPSoC architectures.
Microprocess. Microsystems, 2015

FPGA-based many-core System-on-Chip design.
Microprocess. Microsystems, 2015

Framework for a Selection of Custom Instructions for Ht-MPSoC in Area-performance Aware Manner.
IEEE Embed. Syst. Lett., 2015

Automatic Generation of S-LAM Descriptions from UML/MARTE for the DSE of Massively Parallel Embedded Systems.
Proceedings of the Software Engineering, 2015

Heterogeneous multi-core architecture for a 4G communication in high-speed railway.
Proceedings of the 10th International Design & Test Symposium, 2015

2014
Multi-Softcore Architecture on FPGA.
Int. J. Reconfigurable Comput., 2014

A mixed integer linear programming approach for design space exploration in FPGA-based MPSoC.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Design Space Exploration for Customized Asymmetric Heterogeneous MPSoC.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

MARTE to ΠSDF transformation for data-intensive applications analysis.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

2013
Shared hardware accelerator architectures for heterogeneous MPSoCs.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

Master-Slave Control Structure for Massively Parallel System on Chip.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Mppsocgen: A framework for automatic generation of mppsoc architecture
CoRR, 2012

Broadcast with mask on a massively parallel processing on a chip.
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

Extending MARTE to Support the Specification and the Generation of Data Intensive Applications for Massively Parallel SoC.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
A multi-level design methodology of multistage interconnection network for MPSOCs.
Int. J. Comput. Appl. Technol., 2011

A model-driven based framework for rapid parallel SoC FPGA prototyping.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

2010
Méthode de conception rapide d'architecture massivement parallèle sur puce : de la modélisation à l'expérimentation sur FPGA. (A rapid design method of a massively parallel System on Chip: from modeling to FPGA implementation).
PhD thesis, 2010

Scalable mpNoC for massively parallel systems - Design and implementation on FPGA.
J. Syst. Archit., 2010

Soft-core reduction methodology for SIMD architecture: OPENRISC case study.
Proceedings of the 5th International Design and Test Workshop, 2010

IP Based Configurable SIMD Massively Parallel SoC.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA.
Proceedings of the 7th IEEE/ACS International Conference on Computer Systems and Applications, 2009


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