Mototsugu Hamada
Orcid: 0000-0002-0461-4208
According to our database1,
Mototsugu Hamada
authored at least 83 papers
between 1998 and 2024.
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Bibliography
2024
IEEE J. Solid State Circuits, April, 2024
A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA.
IEICE Trans. Electron., 2024
Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023
Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface.
IEICE Trans. Electron., July, 2023
A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum.
IEEE Micro, 2023
A 7-nm FinFET 1.2-TB/s/mm<sup>2</sup> 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver.
IEEE J. Solid State Circuits, 2023
Guest Editorial Introduction to the Special Issue on the 2022 Symposium on VLSI Circuits.
IEEE J. Solid State Circuits, 2023
A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
An Occlusion-Resilient mmWave Imaging Radar-Based Object Recognition System Using Synthetic Training Data Generation Technique.
Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023
A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multiclass Object Recognition System for ADAS Applications.
IEEE Trans. Instrum. Meas., 2022
A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network.
IEEE Open J. Circuits Syst., 2022
A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC.
IEEE J. Solid State Circuits, 2022
A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique.
Proceedings of the IEEE Sensors Applications Symposium, 2022
Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
A 7-nm FinFET 1.2-TB/s/mm<sup>2</sup> 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
A 5-GHz 0.15-mm<sup>2</sup> Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Introduction to the Special Section on the 2019 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits, 2020
A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A 50 Mbps/pin 12-input/output 40 nsec Latency Wireless Connector Using a Transmission Line Coupler with Compact SERDES IC in 180 nm CMOS.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS.
IEEE J. Solid State Circuits, 2019
IEICE Trans. Electron., 2019
Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Optimization of Resonant Capacitance in Wireless Power Transfer System with 3-D Stacked Two Receivers.
IEICE Trans. Electron., 2018
Fully Integrated OOK-Powered Pad-Less Deep Sub-Wavelength-Sized 5-GHz RFID with On-Chip Antenna Using Adiabatic Logic in 0.18μM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Wireless Power Transfer System for 3-D stacked Multiple Receivers Switching between Single and Dual Frequency Modes.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Comparative Performance Analysis of Dual-Rail Domino Logic and CMOS Logic Under NearThreshold Operation.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Balanced Mini-Batch Training for Imbalanced Image Data Classification with Neural Network.
Proceedings of the First International Conference on Artificial Intelligence for Industries, 2018
2017
Proceedings of the International SoC Design Conference, 2017
Proceedings of the International SoC Design Conference, 2017
2016
Proceedings of the International SoC Design Conference, 2016
2014
4.1 A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2012
A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter.
IEICE Trans. Electron., 2012
2011
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM.
IEEE J. Solid State Circuits, 2011
A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
An all-digital 8-DPSK polar transmitter with second-order approximation scheme and phase rotation-constant digital PA for bluetooth EDR in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010
A 0.13 µm CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation.
IEICE Trans. Electron., 2010
A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
A Novel Automatic Quality Factor Tuning Scheme for a Low-Power Wideband Active-RC Filter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
A 90nm CMOS CT BPF for Bluetooth transceivers with DT 1b-switched-resistor cutoff-frequency control.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 0.6V 380µW -14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
A 19.7 MHz, Fifth-Order Active-RCChebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme.
IEEE J. Solid State Circuits, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 25th International Conference on Computer Design, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
A -90 dBm sensitivity 0.13 μm CMOS bluetooth transceiver operating in wide temperature range.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling.
IEEE J. Solid State Circuits, 2006
Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI.
IEICE Trans. Electron., 2006
2005
IEEE J. Solid State Circuits, 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
IEEE J. Solid State Circuits, 2000
IEEE J. Solid State Circuits, 2000
1998
A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme.
IEEE J. Solid State Circuits, 1998
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques.
Proceedings of the 35th Conference on Design Automation, 1998
A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998