Motoi Inaba

According to our database, Motoi Inaba authored at least 8 papers between 2000 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits.

Motoi Inaba, Koichi Tanno, Hiroki Tamura, Okihiko Ishizuka

IEICE Trans. Inf. Syst., 2010

2009

Optimization of Current-Mode MVD-ORNS Arithmetic Circuits.

Motoi Inaba, Koichi Tanno, Ryota Sawada, Hisashi Tanaka, Hiroki Tamura

Proceedings of the ISMVL 2009, 2009

2007

Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon Process.

Motoi Inaba

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

2006

Linear and Compact Floating Node Voltage-Controlled Variable Resistor Circuit.

Muneo Kushima, Motoi Inaba, Koichi Tanno

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

2002

Analog Inverter with Neuron-MOS Transistors and Its Application.

Motoi Inaba, Koichi Tanno, Okihiko Ishizuka

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits.

Motoi Inaba, Koichi Tanno, Okihiko Ishizuka

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

2001

Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators.

Motoi Inaba, Koichi Tanno, Okihiko Ishizuka

Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

2000

Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors.

Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000