Mostafa M. Ayesh

Orcid: 0000-0002-3814-2288

According to our database1, Mostafa M. Ayesh authored at least 7 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A Blocker-Tolerant Non-Uniform Sub-Sampling Receiver With a Non-Uniform Discrete-Time FIR Filter.
IEEE J. Solid State Circuits, December, 2024

5.3 A 0.072mm<sup>2</sup> 18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2021
26.6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 24-28 GHz Concurrent Harmonic and Subharmonic Tuning Class E/F2, 2/3 Subharmonic Switching Power Amplifier Achieving Peak/PBO Efficiency Enhancement.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2016
Design and analysis of a low-power high-speed charge-steering based StrongARM comparator.
Proceedings of the 28th International Conference on Microelectronics, 2016

2015
A 15.5-mW 20-GSps 4-bit charge-steering flash ADC.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A low-power high-speed charge-steering ADC-based equalizer for serial links.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015


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