Mostafa I. H. Abd-El-Barr
Affiliations:- Kuwait University, Department of Information Sciences, Kuwait
- King Fahd University of Petroleum and Minerals, Department of Computer Engineering, Dhahran, Saudi Arabia
- University of Saskatchewan, Department of Computer Science, Saskatoon, SK, Canada
- University of Toronto, ON, Canada (PhD 1986)
According to our database1,
Mostafa I. H. Abd-El-Barr
authored at least 51 papers
between 1986 and 2014.
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Bibliography
2014
Inf. Sci., 2014
2011
Topological Properties of Hierarchical Interconnection Networks: A Review and Comparison.
J. Electr. Comput. Eng., 2011
2009
Proceedings of the ISMVL 2009, 2009
2008
Corrections to "Design and Performance Analysis of a Unified, Reconfigurable HMAC-Hash Unit" [Dec 07 2683-2695].
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
J. Res. Pract. Inf. Technol., 2008
Proceedings of the 2008 IEEE Swarm Intelligence Symposium, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
Design and analysis of reliablle and fault-tolerant computer systems.
Imperial College Press, ISBN: 978-1-86094-668-4, 2007
2005
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
Fundamentals of computer organization and architecture.
Wiley series on parallel and distributed computing, Wiley, ISBN: 978-0-471-46741-0, 2005
2004
Iterative-Based Minimization of Unary 4-Valued Functions for Current-Mode CMOS Realization.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
Fuzzified ant colony optimization algorithm for efficient combinational circuits synthesis.
Proceedings of the IEEE Congress on Evolutionary Computation, 2004
2003
Proceedings of the IEEE Congress on Evolutionary Computation, 2003
Proceedings of the IEEE Congress on Evolutionary Computation, 2003
Fault Tolerance in Topological Optimization of Computer Networks.
Proceedings of the ISCA 18th International Conference Computers and Their Applications, 2003
2002
Enumerative Techniques in Topological Optimization of Computer Networks Subject to Fault Tolerance and Reliability.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002
On the use of fuzzy logic in a hybrid scheme for tolerating mobile support station failure.
Proceedings of the 2002 IEEE International Conference on Fuzzy Systems, 2002
2001
Clust. Comput., 2001
A New Improved Cost-Table-Based Technique for Synthesis of 4-Valued Unary Functions Implemented Using Current-Mode CMOS Circuits.
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A Hybrid Scheme for Tolerating Mobile Support Station Failures.
Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, 2001
2000
Cost-Analysis of 4-Valued Unary Functions Implemented Using Current-Mode CMOS Circuits.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
1999
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999
Fault Characterization and Testability Considerations in Multi-Valued Logic Circuits.
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999
Proceedings of the IEEE International Conference On Computer Design, 1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
1998
SIGARCH Comput. Archit. News, 1998
Int. J. Commun. Syst., 1998
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
1997
IEEE Netw., 1997
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997
1996
VLSI Design, 1996
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996
1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995
1994
Decomposition-Based Synthesis of Multiple-Valued Functions for Threshold Logic Network Realization.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
1992
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
Incremental Gate: A Method to Compute Minimal Cost CCD Realizations of MVL Functions.
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
1991
IEEE Trans. Computers, 1991
Integrated Specification, Simulation, and Fabrication of Systolic/Wavefront Arrays.
Int. J. Comput. Simul., 1991
A Comparative Study of Programmable Realization Techniques of Multi-Valued Multi-Threshold Functions.
Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991
1990
Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990
Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990
1986
IEEE Trans. Computers, 1986