Mostafa E. Salehi
Orcid: 0000-0003-1733-6056
According to our database1,
Mostafa E. Salehi
authored at least 37 papers
between 2006 and 2024.
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Bibliography
2024
IEEE Embed. Syst. Lett., December, 2024
2023
Fully-Fusible Convolutional Neural Networks for End-to-End Fused Architecture with FPGA Implementation.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Inter-Layer Hybrid Quantization Scheme for Hardware Friendly Implementation of Embedded Deep Neural Networks.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
2022
IEEE Des. Test, 2022
2021
E2BNet: MAC-free yet accurate 2-level binarized neural network accelerator for embedded systems.
J. Real Time Image Process., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Aging-Aware Instruction-Level Statistical Dynamic Timing Analysis for Embedded Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Proceedings of the 28th Euromicro International Conference on Parallel, 2020
MuBiNN: Multi-Level Binarized Recurrent Neural Network for EEG Signal Classification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Instruction-Level NBTI Stress Estimation and Its Application in Runtime Aging Prediction for Embedded Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
2018
Microprocess. Microsystems, 2018
Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints.
J. Electron. Test., 2018
2017
Proceedings of the Big Data and HPC: Ecosystem and Convergence, TopHPC 2017, 2017
2016
A Fast Fault-Tolerant Architecture for Sauvola Local Image Thresholding Algorithm Using Stochastic Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Fast and accurate architectural vulnerability analysis for embedded processors using Instruction Vulnerability Factor.
Microprocess. Microsystems, 2016
Fast and accurate FPGA-based framework for processor architecture vulnerability analysis.
Integr., 2016
2015
J. Supercomput., 2015
2014
Customized pipeline and instruction set architecture for embedded processing engines.
J. Supercomput., 2014
J. Supercomput., 2014
2012
Microelectron. Reliab., 2012
J. Syst. Archit., 2012
Design Space Exploration to Find the Optimum Cache and Register File Size for Embedded Applications
CoRR, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
2011
Dynamic Voltage and Frequency Scheduling for Embedded Processors Considering Power/Performance Tradeoffs.
IEEE Trans. Very Large Scale Integr. Syst., 2011
An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects.
Microelectron. Reliab., 2011
Microelectron. J., 2011
2010
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
2009
Quantitative analysis of packet-processing applications regarding architectural guidelines for network-processing-engine development.
J. Syst. Archit., 2009
2008
Proceedings of the Advances in Computer Science and Engineering, 2008
2006
Dynamic voltage and frequency management based on variable update intervals for frequency setting.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006