Morteza Fayazi

Orcid: 0000-0002-5598-281X

According to our database1, Morteza Fayazi authored at least 15 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication.
ACM Trans. Reconfigurable Technol. Syst., December, 2024

2023
AnGeL: Fully-Automated Analog Circuit Generator Using a Neural Network Assisted Semi-Supervised Learning Approach.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

Open Information Extraction: A Review of Baseline Techniques, Approaches, and Applications.
CoRR, 2023

FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

A Compact CMOS 363 GHz Autodyne FMCW Radar with 57 GHz Bandwidth for Dental Imaging.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
FASCINET: A Fully Automated Single-Board Computer Generator Using Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory.
IEEE J. Solid State Circuits, 2022

Tablext: A combined neural network and heuristic based table extractor.
Array, 2022

A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation.
Proceedings of the VLSI-SoC: Design Trends, 2020

An Open-source Framework for Autonomous SoC Design with Analog Block Generation.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

2019
A Simplified Approach to Two-Port Analysis in Feedback.
CoRR, 2019

2017
Structural relations between brain-behavioral systems, social anxiety, depression and internet addiction: With regard to revised Reinforcement Sensitivity Theory (r-RST).
Comput. Hum. Behav., 2017


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