Moritz Schmid

According to our database1, Moritz Schmid authored at least 21 papers between 2008 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Loop Parallelization Techniques for FPGA Accelerator Synthesis.
J. Signal Process. Syst., 2018

Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution.
Parallel Process. Lett., 2018

2017
A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators.
J. Signal Process. Syst., 2017

2016
Big Data and HPC Acceleration with Vivado HLS.
Proceedings of the FPGAs for Software Programmers, 2016

HIPA<sup>cc</sup>.
Proceedings of the FPGAs for Software Programmers, 2016

2015
Rapid Prototyping for Hardware Accelerators in the Medical Imaging Domain.
PhD thesis, 2015

Synthesis and optimization of image processing accelerators using domain knowledge.
J. Syst. Archit., 2015

Loop coarsening in C-based High-Level Synthesis.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs.
CoRR, 2014

An image processing library for C-based high-level synthesis.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Code generation from a domain-specific language for C-based HLS of hardware accelerators.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Domain-specific augmentations for High-Level Synthesis.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
Real-timerange image preprocessing on FPGAs.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model.
Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013

System integration of tightly-coupled processor arrays using reconfigurable buffer structures.
Proceedings of the Computing Frontiers Conference, 2013

2012
Hierarchical power management for adaptive tightly-coupled processor arrays.
ACM Trans. Design Autom. Electr. Syst., 2012

Power Management Strategies for Serial RapidIO Endpoints in FPGAs.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011
RITK: The Range Imaging Toolkit - A Framework for 3-D Range Image Stream Processing.
Proceedings of the 16th International Workshop on Vision, Modeling, and Visualization, 2011

2010
A deeply pipelined and parallel architecture for denoising medical images.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Modeling and synthesis of communication subsystems for loop accelerator pipelines.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2008
Netlist-level IP protection by watermarking for LUT-based FPGAs.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008


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