Moritz Brunion

According to our database, Moritz Brunion authored at least 15 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

On Legalization of Die Bonding Bumps and Pads for 3-D ICs.

Yen-Hsiang Huang, Sai Pentapati, Anthony Agnesina, Moritz Brunion, Sung Kyu Lim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2024

Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs.

Nesara Eranna Bethur, Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024

Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits.

Yun Zhou, S. C. Song, Halil Kükner, Giuliano Sisto, Sheng Yang, Anita Farokhnejad, Mohamed Naeim, Moritz Brunion, Ji-Yung Lin, Odysseas Zografos, Pieter Weckx, Shashank Ekbote, Nick Stevens-Yu, David Greenlaw, Steve Molloy, Geert Hellings, Julien Ryckaert

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5).

S. Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, Gioele Mirabelli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs.

Sudipta Das, Samuel Riedel, Marco Bertuletti, Luca Benini, Moritz Brunion, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation.

Subrat Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, A. Sharma, G. Mirabeli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert

Proceedings of the IEEE International Reliability Physics Symposium, 2024

Thermal Analysis of High-Performance Server SoCs from FinFET to Nanosheet Technologies.

Nitish Kumar, Sankatali Venkateswarlu, Yukai Chen, Moritz Brunion, Subrat Mishra, Ankur Gupta, Pushpapraj Singh, Francky Catthoor, James Myers, Julien Ryckaert, Dwaipayan Biswas

Proceedings of the IEEE International Reliability Physics Symposium, 2024

2023

Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC.

Sankatali Venkateswarlu, Subrat Mishra, Herman Oprins, Bjorn Vermeersch, Moritz Brunion, Jun-Han Han, Mircea R. Stan, Dwaipayan Biswas, Pieter Weckx, Francky Catthoor

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

On Legalization of Die Bonding Bumps and Pads for 3D ICs.

Sai Pentapati, Anthony Agnesina, Moritz Brunion, Yen-Hsiang Huang, Sung Kyu Lim

Proceedings of the 2023 International Symposium on Physical Design, 2023

Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs).

Subrat Mishra, Sankatali Venkateswarlu, Bjorn Vermeersch, Moritz Brunion, Melina Lofrano, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Gaspard Hiblot, Geert Van der Plas, Pieter Weckx, Geert Hellings, James Myers, Francky Catthoor, Julien Ryckaert

Proceedings of the IEEE International Reliability Physics Symposium, 2023

Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs.

Mohamed Naeim, Hanqi Yang, Pinhong Chen, Rong Bao, Antoine Dekeyser, Giuliano Sisto, Moritz Brunion, Rongmei Chen, Geert Van der Plas, Eric Beyne, Dragomir Milojevic

Proceedings of the IEEE International 3D Systems Integration Conference, 2023

2022

Thermal Performance Analysis of Mempool RISC-V Multicore SoC.

Sankatali Venkateswarlu, Subrat Mishra, Herman Oprins, Bjorn Vermeersch, Moritz Brunion, Jun-Han Han, Mircea R. Stan, Pieter Weckx, Francky Catthoor

IEEE Trans. Very Large Scale Integr. Syst., 2022

Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs.

Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration.

Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs.

Anthony Agnesina, Moritz Brunion, Jinwoo Kim, Alberto García Ortiz, Dragomir Milojevic, Francky Catthoor, Manu Perumkunnil, Sung Kyu Lim

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021