Morihiro Kuga

According to our database, Morihiro Kuga authored at least 45 papers between 1989 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks.

Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2024

2023

An eFPGA Generation Suite with Customizable Architecture and IDE.

Morihiro Kuga, Qian Zhao, Yuya Nakazato, Motoki Amagasaki, Masahiro Iida

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023

2022

FPL Demo: An FPGA-IP Prototype Chip for MEC devices.

Morihiro Kuga, Masahiro Iida, Hideharu Amano

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021

Automation of Domain-specific FPGA-IP Generation and Test.

Yuya Nakazato, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga

Proceedings of the HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021

2018

Enabling FPGA-as-a-Service in the Cloud with hCODE Platform.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2018

2017

Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IPSJ Trans. Syst. LSI Des. Methodol., 2017

Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core.

Motoki Amagasaki, Yuki Nishitani, Kazuki Inoue, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2017

High-level Synthesis based on Parallel Design Patterns using a Functional Language.

Morihiro Kuga, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

FPGA based ASIC Emulator with High Speed Optical Serial Links.

Motoki Amagasaki, Futoshi Murase, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds.

Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the International Conference on Field Programmable Technology, 2017

2016

A Study of Heterogeneous Computing Design Method based on Virtualization Technology.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

SIGARCH Comput. Archit. News, 2016

hCODE: An open-source platform for FPGA accelerators.

Qian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015

A 3D FPGA Architecture to Realize Simple Die Stacking.

Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IPSJ Trans. Syst. LSI Des. Methodol., 2015

Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC.

Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2015

Architecture exploration of 3D FPGA to minimize internal layer connection.

Motoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Simple wafer stacking 3D-FPGA architecture.

Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014

Blokus Duo engine on a Zynq.

Susumu Mashimo, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Zyndroid: An Android platform for software/hardware coprocessing.

Susumu Mashimo, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory.

Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013

A reconfigurable Java accelerator with software compatibility for embedded systems.

Yuki Ogawa, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi

SIGARCH Comput. Archit. News, 2013

FPGA Design Framework Combined with Commercial VLSI CAD.

Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEICE Trans. Inf. Syst., 2013

Three-dimensional stacking FPGA architecture using face-to-face integration.

Tetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

An FPGA design and implementation framework combined with commercial VLSI CADs.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

An automatic FPGA design and implementation framework.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Defect-robust FPGA architectures for intellectual property cores in system LSI.

Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A novel FPGA design framework with VLSI post-routing performance analysis (abstract only).

Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012

Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration.

Yoshihiro Ichinomiya, Tsuyoshi Kimura, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Evaluation of fault tolerant technique based on homogeneous FPGA architecture.

Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

A novel physical defects recovery technique for FPGA-IP cores.

Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration.

Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the Algorithms and Architectures for Parallel Processing, 2012

Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration.

Makoto Fujino, Hiroki Tanaka, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the Algorithms and Architectures for Parallel Processing, 2012

Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration.

Yoshihiro Ichinomiya, Kohei Takano, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Fault detection and avoidance of FPGA in various granularities.

Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams.

Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011

Parallelization of the channel width search for FPGA routing.

Hiroomi Sawada, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

SIGARCH Comput. Archit. News, 2011

Improving the Soft-error Tolerability of a Soft-core Processor on.

Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

J. Next Gener. Inf. Technol., 2011

2010

Power-aware FPGA routing fabrics and design tools.

Shoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration.

Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

2009

A novel states recovery technique for the TMR softcore processor.

Shiro Tanoue, Tomoyuki Ishida, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Memory Sharing Approach for TMR Softcore Processor.

Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the Reconfigurable Computing: Architectures, 2009

2004

EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA.

Hidetomo Shibamura, Masayuki Fukuyama, Daisuke Uchida, Seiji Ikeda, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

2002

KITE microprocessor and CAE for computer science.

Toshinori Sueyoshi, Morihiro Kuga, Hidetomo Shibamura

Syst. Comput. Jpn., 2002

1994

Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations.

Kei Hiraki, Hideharu Amano, Morihiro Kuga, Toshinori Sueyoshi, Tomohiro Kudoh, Hiroshi Nakashima, Hironori Nakajo, Hideo Matsuda, Takashi Matsumoto, Shin-ichiro Mori

Proceedings of the International Symposium on Parallel Architectures, 1994

1991

DSNS (dynamically-hazard-resolved statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture.

Morihiro Kuga, Kazuaki J. Murakami, Shinji Tomita

SIGARCH Comput. Archit. News, 1991

1989

SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture.

Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita

Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989