Moon-Chul Choi
Orcid: 0000-0001-9100-1559
According to our database1,
Moon-Chul Choi
authored at least 10 papers
between 2017 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
2021
A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS.
IEEE Access, 2021
A Maximum Eye Tracking Clock-and-Data Recovery Scheme with Golden Section Search(GSS) Algorithm in 28-nm CMOS.
Proceedings of the 18th International SoC Design Conference, 2021
2020
A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019
2018
A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2017
A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and G<sub>m</sub>-Regulated Resistive-Feedback Driver.
IEEE Trans. Circuits Syst. II Express Briefs, 2017