Monther Abusultan

According to our database1, Monther Abusultan authored at least 16 papers between 2014 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Hardware Acceleration of Hash Operations in Modern Microprocessors.
IEEE Trans. Computers, 2021

2018
Comparing Leakage Reduction Techniques for an Asynchronous Network-on-Chip Router.
J. Low Power Electron., 2018

2017
Circuit Level Design of a Hardware Hash Unit for use in Modern Microprocessors.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Design of a Flash-based Circuit for Multi-valued Logic.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
FTCAM: An Area-Efficient Flash-Based Ternary CAM Design.
IEEE Trans. Computers, 2016

A Ternary-Valued, Floating Gate Transistor-Based Circuit Design Approach.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A novel hardware hash unit design for modern microprocessors.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Exploring static and dynamic flash-based FPGA design topologies.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Implementing low power digital circuits using flash devices.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

A flash-based digital circuit design flow.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A GPU-based implementation of a sensor tasking methodology.
Proceedings of the 19th International Conference on Information Fusion, 2016

2015
Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAs.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
An area-efficient Ternary CAM design using floating gate transistors.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

A comparison of FinFET based FPGA LUT designs.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

FPGA LUT design for wide-band dynamic voltage and frequency scaled operation (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Look-up Table Design for Deep Sub-threshold through Full-Supply Operation.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014


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