Monodeep Kar
Orcid: 0000-0002-9318-6793Affiliations:
- Georgia Institute of Technology, Atlanta, GA, USA
According to our database1,
Monodeep Kar
authored at least 47 papers
between 2014 and 2024.
Collaborative distances:
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Bibliography
2024
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.
IEEE J. Solid State Circuits, 2022
2021
IEEE J. Solid State Circuits, 2021
IEEE Internet Things J., 2021
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Proceedings of the 13th International Conference on Computer and Automation Engineering, 2021
Methodology of Assessing Information Leakage through Software-Accessible Telemetries.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021
2020
An Inductive Voltage Regulator With Overdrive Tracking Across Input Voltage in Cascoded Power Stage.
IEEE Trans. Circuits Syst., 2020
Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO.
IEEE J. Solid State Circuits, 2020
A 4900- $\mu$ m<sup>2</sup> 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition.
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering.
IEEE J. Solid State Circuits, 2019
IEEE Internet Things J., 2019
Multigated Carbon Nanotube Field Effect Transistors-Based Physically Unclonable Functions As Security Keys.
IEEE Internet Things J., 2019
A 4900×m<sup>2</sup> 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the International Joint Conference on Neural Networks, 2019
Extracting Side-Channel Leakage from Round Unrolled Implementations of Lightweight Ciphers.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
Mitigating Power Supply Glitch based Fault Attacks with Fast All-Digital Clock Modulation Circuit.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator.
IEEE J. Solid State Circuits, 2018
Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator.
CoRR, 2018
Energy efficient and side-channel secure hardware architecture for lightweight cipher SIMON.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Performance based tuning of an inductive integrated voltage regulator driving a digital core against process and passive variations.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
An All-Digital Fully Integrated Inductive Buck Regulator With A 250-MHz Multi-Sampled Compensator and a Lightweight Auto-Tuner in 130-nm CMOS.
IEEE J. Solid State Circuits, 2017
Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators.
J. Hardw. Syst. Secur., 2017
8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Invited paper: Low power requirements and side-channel protection of encryption engines: Challenges and opportunities.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
A case for low frequency single cycle multi hop NoCs for energy efficiency and high performance.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2016
Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Integrated all-digital low-dropout regulator as a countermeasure to power attack in encryption engines.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016
An integrated inductive VR with a 250MHz all-digital multisampled compensator and on-chip auto-tuning of coefficients in 130nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
2014
Impact of process variation in inductive integrated voltage regulator on delay and power of digital circuits.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014