Mona Safar

Orcid: 0000-0002-1696-1792

Affiliations:
  • Ain Shams University, Egypt


According to our database1, Mona Safar authored at least 43 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Adaptive SAT Modeling for Optimal Pattern Retargeting in IEEE 1687 Networks.
IEEE Trans. Computers, February, 2024

Non-Invasive Hardware Trojans Modeling and Insertion: A Formal Verification Approach.
J. Electron. Test., February, 2024

2023
Hardware-accelerated service-oriented communication for AUTOSAR platforms.
Des. Autom. Embed. Syst., September, 2023

Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation.
ACM Trans. Design Autom. Electr. Syst., July, 2023

Hardware Security Analysis of Arbiters: Trojan Modeling and Formal Verification.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

A Novel Architecture of CXL Protocol Data Link Layer for Low Latency Memory Access.
Proceedings of the International Conference on Microelectronics, 2023

2022
A Multicycle Pipelined GCM-Based AUTOSAR Communication ASIP.
IEEE Access, 2022

An Evaluation Method for Embedded Software Dependability Using QEMU-Based Fault Injection Framework.
Proceedings of the 6th International Conference on System Reliability and Safety, 2022

A Reusable UVM-SystemC Verification Environment for Simulation, Hardware Emulation, and FPGA Prototyping: Case Studies.
Proceedings of the International Conference on Microelectronics, 2022

Optimized FPGA Architecture for Machine Learning Applications using Posit Multipliers.
Proceedings of the International Conference on Microelectronics, 2022

2020
Verification of Neural Networks for Safety Critical Applications.
Proceedings of the 32nd International Conference on Microelectronics, 2020

Hardware-accelerated SOME/IP-based Serialization for AUTOSAR Platforms.
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

A High-Accuracy Implementation for Softmax Layer in Deep Neural Networks.
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

Anomaly Detection System for Altered Signal Values within the Intra-Vehicle Network.
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

2019
Fast Transaction-Level Model for Direct Memory Access Controller.
J. Circuits Syst. Comput., 2019

Virtual Verification and Validation of Automotive System.
J. Circuits Syst. Comput., 2019

Efficient Structured Scan Patterns Retargeting for Hierarchical IEEE 1687 Networks.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Symbolic Execution based Verification of Compliance with the ISO 26262 Functional Safety Standard.
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

2018
Virtual Electronic Control Unit as a Functional Mockup Unit for Heterogeneous Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Formal Verification of AUTOSAR Watchdog Manager Module Using Symbolic Execution.
Proceedings of the 30th International Conference on Microelectronics, 2018

2017
A kernel-based solution for overload in mixed criticality multicore systems.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2017

Asil decomposition using SMT.
Proceedings of the 2017 Forum on Specification and Design Languages, 2017

Bloom filter acceleration: A high level synthesis approach.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016
Accelerating iterative protein sequence alignment on a heterogeneous GPU-CPU platform.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

AUTOSAR-based communication coprocessor for automotive ECUs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
SystemVerilog assertion debugging: A visualization and pattern matching model.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015

Toward the interfacing of systemC-AMS models with hardware-emulated platforms.
Proceedings of the 10th International Design & Test Symposium, 2015

Automatic test pattern generation for virtual hardware model using constrained symbolic execution.
Proceedings of the 10th International Design & Test Symposium, 2015

Solving constraints in FPGA detailed routing using SMT.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014
Don't cares based dynamic test vector compaction in SAT-ATPG.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation.
Proceedings of the 15th International Microprocessor Test and Verification Workshop, 2014

Efficient embedded SoC hardware/software codesign using virtual platform.
Proceedings of the 9th International Design and Test Symposium, 2014

2013
Ultra-Fast DMAC TLM Model for High Speed Virtual Platform Simulation.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

2011
TLM Based Approach for Architecture Exploration of Multicore Systems-on-Chip.
Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011

A reconfigurable, pipelined, conflict directed jumping search SAT solver.
Proceedings of the Design, Automation and Test in Europe, 2011

A novel approach for system level synthesis of multi-core system architectures from TPG models.
Proceedings of the 9th IEEE/ACS International Conference on Computer Systems and Applications, 2011

2010
A novel conflict directed jumping algorithm for hardware-based SAT solvers.
Proceedings of the 5th International Design and Test Workshop, 2010

2009
A Reconfigurable Five-Stage Pipelined SAT Solver.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

2008
Hardware based algorithm for conflict diagnosis in SAT solver.
Proceedings of the 6th ACS/IEEE International Conference on Computer Systems and Applications, 2008

2007
Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
FPGA-Based SAT Solver.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2005
An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers.
Proceedings of the Correct Hardware Design and Verification Methods, 2005


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