Mohsen Saneei

According to our database, Mohsen Saneei authored at least 16 papers between 2006 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Evaluation of multi-level Bang-Bang phase detector with metastability effect using Markov chain.

Sanaz Salem, Mohsen Saneei, Dariush Abbasi-Moghadam

Microelectron. J., 2021

Jitter Modeling in Digital CDR with Quantization Noise Analysis.

Sanaz Salem, Mohsen Saneei, Dariush Abbasi-Moghadam

Circuits Syst. Signal Process., 2021

2020

Jitter and metastability analysis and modeling of multilevel bang-bang phase detector.

Sanaz Salem, Mohsen Saneei, Dariush Abbasi-Moghadam

Int. J. Circuit Theory Appl., 2020

2019

Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications.

Shirin Askari, Mohsen Saneei

Int. J. Circuit Theory Appl., 2019

All-digital delay line-based time difference amplifier in 65 nm CMOS technology.

Ramin Razmdideh, Mohsen Saneei

IET Circuits Devices Syst., 2019

2018

Low-power, latch-based multistage time-to-digital converter in 65 nm CMOS technology.

Ramin Razmdideh, Mohsen Saneei

Int. J. Circuit Theory Appl., 2018

Fault-tolerant delay cell for ring oscillator application in 65 nm CMOS technology.

Sanaz Salem, Hamed Zandevakili, Ali Mahani, Mohsen Saneei

IET Circuits Devices Syst., 2018

2015

New Design of Scan Flip-Flop to Increase Speed and Reduce Power Consumption.

Ramin Razmdideh, Ali Mahani, Mohsen Saneei

J. Circuits Syst. Comput., 2015

Two novel low power and very high speed pulse triggered flip-flops.

Ramin Razmdideh, Mohsen Saneei

Int. J. Circuit Theory Appl., 2015

A novel low power and high speed double edge explicit pulse triggered level converter flip-flop.

Ramin Razmdideh, Mohsen Saneei

Int. J. Circuit Theory Appl., 2015

Time-to-digital convertor based on resolution control.

Asma Dehghani, Mohsen Saneei, Ali Mahani

IET Circuits Devices Syst., 2015

2013

Probabilistic Transfer Matrix with mixed Binary-Decimal Coding for Logic Circuit Reliability Analysis.

Hamed Zandevakili, Ali Mahani, Mohsen Saneei

J. Circuits Syst. Comput., 2013

2009

Sign Bit Reduction Encoding For Low Power Applications.

Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi

J. Signal Process. Syst., 2009

2007

Fast INC-XOR codec for low-power address buses.

Hadi Parandeh-Afshar, Mohsen Saneei, Ali Afzali-Kusha, Massoud Pedram

IET Comput. Digit. Tech., 2007

2006

Serial Bus Encoding for Low Power Application.

Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi

Proceedings of the International Symposium on System-on-Chip, 2006

Low-power and low-latency cluster topology for local traffic NoCs.

Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006