Mohit Sharma

According to our database, Mohit Sharma authored at least 3 papers between 2016 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance.

Satish Maheshwaram, Om. Prakash, Mohit Sharma, Anand Bulusu, Sanjeev Manhas

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2016

A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation.

Om. Prakash, Satish Maheshwaram, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

Lateral silicon nanowire based standard cell design for higher performance.

Om. Prakash, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas, Satish Maheshwaram

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016