Mohit Gupta

Orcid: 0000-0002-1924-1264

Affiliations:
  • imec, Leuven, Belgium
  • KU Leuven, Department ESAT-MICAS, Belgium
  • Aligarh Muslim University, Department of Electronics Engineering, India


According to our database1, Mohit Gupta authored at least 14 papers between 2016 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs.
IEEE Trans. Very Large Scale Integr. Syst., June, 2024

2023
Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

Impact of interconnects enhancement on SRAM design beyond 5nm technology node.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022
Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices.
ACM Trans. Embed. Comput. Syst., 2022

A Soft SIMD Based Energy Efficient Computing Microarchitecture.
CoRR, 2022

Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022

CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2017
Low Leakage Single Bitline 9 T (SB9T) Static Random Access Memory.
Microelectron. J., 2017

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016
A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell.
IEEE Trans. Very Large Scale Integr. Syst., 2016


  Loading...