Mohammed Nabeel Thari Moopan
Orcid: 0000-0002-3924-7356Affiliations:
- New York University Abu Dhabi (NYU Abu Dhabi), Division of Engineering, United Arab Emirates
According to our database1,
Mohammed Nabeel Thari Moopan
authored at least 38 papers
between 2017 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024
Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2024
NiLoPher: Breaking a Modern SAT-Hardened Logic-Locking Scheme via Power Analysis Attack.
IACR Cryptol. ePrint Arch., 2024
ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search.
CoRR, 2024
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Exploring Constrained-Modulus Modular Multipliers for Improved Area, Power and Flexibility.
Proceedings of the VLSI-SoC 2023: Innovations for Trustworthy Artificial Intelligence, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks.
Proceedings of the 2023 International Symposium on Physical Design, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
IEEE Trans. Emerg. Top. Comput., 2022
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology.
Integr., 2022
Cryptogr., 2022
SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
2021
IACR Cryptol. ePrint Arch., 2021
Toward Security Closure in the Face of Reliability Effects ICCAD Special Session Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Computers, 2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
2019
ACM Trans. Design Autom. Electr. Syst., 2019
IACR Cryptol. ePrint Arch., 2019
An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets.
CoRR, 2019
Power, Area, Speed, and Security (PASS) Trade-Offs of NIST PQC Signature Candidates Using a C to ASIC Design Flow.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
2017
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017