MohammadReza Taheri
Orcid: 0000-0003-3764-7599
According to our database1,
MohammadReza Taheri
authored at least 13 papers
between 2010 and 2023.
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Bibliography
2023
Efficient realization of quantum balanced ternary reversible multiplier building blocks: A great step towards sustainable computing.
Sustain. Comput. Informatics Syst., December, 2023
2022
ReFACE: Efficient Design Methodology for Acceleration of Digital Filter Implementations.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Processing-in-Memory Acceleration of MAC-based Applications Using Residue Number System: A Comparative Study.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
2020
A novel majority based imprecise 4: 2 compressor with respect to the current and future VLSI industry.
Microprocess. Microsystems, 2020
2019
Toward efficient implementation of basic balanced ternary arithmetic operations in CNFET technology.
Microelectron. J., 2019
Novel CNFET ternary circuit techniques for high-performance and energy-efficient design.
IET Circuits Devices Syst., 2019
2018
2017
J. Low Power Electron., 2017
2014
Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style.
Integr., 2014
2012
Efficient RNS to binary converters for the new 4-moduli set {2<sup><i>n</i></sup>, 2<sup><i>n</i>+1</sup>-1, 2<sup><i>n</i></sup>-1, 2<sup><i>n</i>-1</sup>-1}.
IEICE Electron. Express, 2012
2010
High speed reverse converter for new five-moduli set {2<sup>n</sup>, 2<sup>2n+1</sup>-1, 2<sup>n/2</sup>-1, 2<sup>n/2</sup>+1, 2<sup>n</sup>+1}.
IEICE Electron. Express, 2010