Mohammad Taherzadeh-Sani
Orcid: 0000-0002-0288-6293
According to our database1,
Mohammad Taherzadeh-Sani
authored at least 44 papers
between 2003 and 2023.
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Bibliography
2023
A Compact Wideband Two-Stage LNA with Multiple Notches for Out-of-Band Filtering Using Center-Tap Inductors.
Circuits Syst. Signal Process., May, 2023
IEEE Trans. Instrum. Meas., 2023
An Energy Efficient Coherent IR-UWB Receiver With Non-Coherent-Assisted Synchronization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
2021
A 22-Gb/s Time-Interleaved Low-Power Optical Receiver With a Two-Bit Integrating Front End.
IEEE J. Solid State Circuits, 2021
2020
A 17 Gbps 156 fJ/bit Two-Channel Optical Receiver With Optical-Input Split and Delay in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
An Algebraic Approach to Fast Estimation of the Threshold Voltage of Junctionless Double Gate MOSFETs Using the Gram Schmidt Method.
CoRR, 2019
2018
A 0.8-4-GHz Software-Defined Radio Receiver With Improved Harmonic Rejection Through Non-Overlapped Clocking.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Envelope-tracking common-drain CMOS power amplifier with a switching-only supply modulator for LTE applications.
Microelectron. J., 2018
2017
A 170-dB Ω CMOS TIA With 52-pA Input-Referred Noise and 1-MHz Bandwidth for Very Low Current Sensing.
IEEE Trans. Very Large Scale Integr. Syst., 2017
65 nm CMOS switching discontinuous-conduction mode buck converter with 330 ns start-up time for light-load power-cycled applications.
IET Circuits Devices Syst., 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
A 27 mV output ripple 92% efficiency buck converter using a multi-bit delta-sigma modulator controller and segmented output switch in 180 nm CMOS.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Single-ended impedance-modulation equalization for low-power differential voltage-mode drivers.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2015
A 350-MS/s Continuous-Time Delta-Sigma Modulator With a Digitally Assisted Binary-DAC and a 5-Bits Two-Step-ADC Quantizer in 130-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
A 1-V 690 μW 8-bit 200 MS/s flash-SAR ADC with pipelined operation of flash and SAR ADCs in 0.13μm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
A 10-bit 110 kS/s 1.16 µW SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
2013
A Reconfigurable and Power-Scalable 10-12 Bit 0.4-44 MS/s Pipelined ADC With 0.35-0.5 pJ/Step in 1.2 V 90 nm Digital CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
2012
Correction to "A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS" [Mar 11 660-668].
IEEE J. Solid State Circuits, 2012
2011
A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS.
IEEE J. Solid State Circuits, 2011
2010
Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2010
A reconfigurable 10-12b 0.4-44MS/s pipelined ADC with 0.35-0.5pJ/step in 1.2V 90nm digital CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Behavioral modeling of Opamp gain and dynamic effectsfor power optimization of Delta-Sigma modulators and pipelined ADCs.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Digital background calibration of interstage-gain and capacitor-mismatch errors in pipelined ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A 12-bit 40MSPS 3.3-V 56-mW pipelined A/D convereter in 0.25-µm CMOS [convereter read converter].
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 Design, 2004
2003
Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications.
Integr., 2003
A low-power design methodology for high-resolution pipelined analog-to-digital converters.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
An analytical approach to the estimation of the spurious-free dynamic range in pipeline A/D converters.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
A 1.5-V 12-bit 75M-samples/s fully-differential low-power sample-and-hold amplifier in 0.25-μm CMOS.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
An analytical approach to the estimation of dynamic non-linearity parameters in pipeline A/D converters.
Proceedings of the ESSCIRC 2003, 2003