Mohammad Shihabul Haque
Orcid: 0000-0002-5977-8533
According to our database1,
Mohammad Shihabul Haque
authored at least 11 papers
between 2009 and 2018.
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Bibliography
2018
Predictability and Performance Aware Replacement Policy PVISAM for Unified Shared Caches in Real-time Multicores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Computer, 2018
A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems.
Proceedings of the 21st IEEE International Symposium on Real-Time Distributed Computing, 2018
2015
Accelerating non-volatile/hybrid processor cache design space exploration for application specific embedded systems.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2013
TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
2011
CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
2010
Proceedings of the Design, Automation and Test in Europe, 2010
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy.
Proceedings of the Design, Automation and Test in Europe, 2010
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.
Proceedings of the 47th Design Automation Conference, 2010
2009
SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009