Mohammad Saeed Ansari
Orcid: 0000-0001-7792-359X
According to our database1,
Mohammad Saeed Ansari
authored at least 16 papers
between 2012 and 2024.
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Bibliography
2024
Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
2022
IEEE Trans. Emerg. Top. Comput., 2022
2021
IEEE Trans. Computers, 2021
Strengthened 32-bit AES implementation: Architectural error correction configuration with a new voting scheme.
IET Comput. Digit. Tech., 2021
IET Comput. Digit. Tech., 2021
Hardware acceleration of the novel two dimensional Burrows-Wheeler Aligner algorithm with maximal exact matches seed extension kernel.
IET Circuits Devices Syst., 2021
A Logarithmic Floating-Point Multiplier for the Efficient Training of Neural Networks.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
2020
Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers.
IEEE Trans. Very Large Scale Integr. Syst., 2020
2019
Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Approximate Leading One Detector Design for a Hardware-Efficient Mitchell Multiplier.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019
2018
Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
2016
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016
2013
Energy-efficient network design via modelling: optimal designing point for energy, reliability, coverage and end-to-end delay.
IET Networks, 2013
2012
Proceedings of the 8th International Symposium on Communication Systems, 2012