Mohammad Sadrosadati
Orcid: 0000-0002-4029-0175
According to our database1,
Mohammad Sadrosadati
authored at least 71 papers
between 2015 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
Proteus: Achieving High-Performance Processing-Using-DRAM via Dynamic Precision Bit-Serial Arithmetic.
CoRR, January, 2025
2024
PyGim : An Efficient Graph Neural Network Library for Real Processing-In-Memory Architectures.
Proc. ACM Meas. Anal. Comput. Syst., December, 2024
ACM Trans. Archit. Code Optim., September, 2024
ACM Trans. Design Autom. Electr. Syst., May, 2024
Proc. ACM Meas. Anal. Comput. Syst., 2024
Amplifying Main Memory-Based Timing Covert and Side Channels using Processing-in-Memory Operations.
CoRR, 2024
Analysis of Distributed Optimization Algorithms on a Real Processing-In-Memory System.
CoRR, 2024
RawAlign: Accurate, Fast, and Scalable Raw Nanopore Signal Mapping via Combining Seeding and Alignment.
IEEE Access, 2024
Proceedings of the Abstracts of the 2024 ACM SIGMETRICS/IFIP PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems, 2024
SwiftRL: Towards Efficient Reinforcement Learning on Real Processing-In-Memory Systems.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2024
MegIS: High-Performance, Energy-Efficient, and Low-Cost Metagenomic Analysis with In-Storage Processing.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis.
Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2024
An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips.
Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2024
PIM-Opt: Demystifying Distributed Optimization Algorithms on a Real-World Processing-In-Memory System.
Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques, 2024
2023
IEEE Trans. Emerg. Top. Comput., 2023
PULSAR: Simultaneous Many-Row Activation for Reliable and High-Performance Computing in Off-the-Shelf DRAM Chips.
CoRR, 2023
CoRR, 2023
TransPimLib: A Library for Efficient Transcendental Functions on Processing-in-Memory Systems.
CoRR, 2023
Proceedings of the International Symposium on Computer Architecture and High Performance Computing Workshops , 2023
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023
Venice: Improving Solid-State Drive Parallelism at Low Cost via Conflict-Free Accesses.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
2022
Dataset, July, 2022
Proc. ACM Meas. Anal. Comput. Syst., 2022
TargetCall: Eliminating the Wasted Computation in Basecalling via Pre-Basecalling Filtering.
CoRR, 2022
RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory.
CoRR, 2022
Adv. Comput., 2022
Chapter Three - A power-performance balanced network-on-chip for mixed CPU-GPU systems.
Adv. Comput., 2022
GenPIP: In-Memory Acceleration of Genome Analysis via Tight Integration of Basecalling and Read Mapping.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Morpheus: Extending the Last Level Cache Capacity in GPU Systems Using Idle GPU Core Resources.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
2021
ACM Trans. Archit. Code Optim., 2021
pLUTo: In-DRAM Lookup Tables to Enable Massively Parallel General-Purpose Computation.
CoRR, 2021
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks.
IEEE Access, 2021
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
2020
Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation.
CoRR, 2020
IEEE Comput. Archit. Lett., 2020
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
2019
ACM Trans. Comput. Syst., 2019
IEEE Trans. Computers, 2019
ACM Trans. Archit. Code Optim., 2019
Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch Boxes.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
2018
ACM Trans. Parallel Comput., 2018
CoRR, 2018
Enabling Efficient RDMA-based Synchronous Mirroring of Persistent Memory Transactions.
CoRR, 2018
IEEE Comput. Archit. Lett., 2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
Proceedings of the 16th USENIX Conference on File and Storage Technologies, 2018
LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
2017
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017
2016
Proceedings of the 24th Euromicro International Conference on Parallel, 2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Quantifying the difference in resource demand among classic and modern NoC workloads.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2015
An efficient DVS scheme for on-chip networks using reconfigurable Virtual Channel allocators.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015