Mohammad Sadegh Jalali

According to our database, Mohammad Sadegh Jalali authored at least 11 papers between 2010 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support.

Mohammad Sadegh Jalali, Mohammad Hossein Taghavi, Angus McLaren, Jennifer Pham, Kamran Farzan, Dominic DiClemente, Marcus van Ierssel, William Song, Saman Asgaran, Chris D. Holdenried, Saman Sadr

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

High speed ADCs for wireline applications.

Mohammad Sadegh Jalali, Masum Hossain, Kenneth Dyer, Saman Sadr

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2015

A 3x blind ADC-based CDR for a 20 dB loss channel.

Mohammad Sadegh Jalali, Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs.

Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

IEEE J. Solid State Circuits, 2015

A Reference-Less Single-Loop Half-Rate Binary CDR.

Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

IEEE J. Solid State Circuits, 2015

2014

An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset".

Ravi Shivnaraine, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs.

Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

Proceedings of the Symposium on VLSI Circuits, 2014

A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE.

Clifford Ting, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection.

Mohammad Sadegh Jalali, Ravi Shivnaraine, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011

A hybrid phase-locked loop for CDR Applications.

Mohammad Sadegh Jalali, Alireza Sharif Bakhtiar, Shahriar Mirabbasi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

An RF power harvesting system with input-tuning for long-range RFID tags.

Alireza Sharif Bakhtiar, Mohammad Sadegh Jalali, Shahriar Mirabbasi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010