Mohammad Mortazavi

According to our database1, Mohammad Mortazavi authored at least 16 papers between 1995 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2014
Audio-visual speech recognition techniques in augmented reality environments.
Vis. Comput., 2014

CPM: A congestion control method for interplanetary network.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

2012
Using augmented reality and automatic speech recognition techniques to help deaf and hard of hearing people.
Proceedings of the Virtual Reality International Conference, 2012

Combining Augmented Reality and Speech Technologies to Help Deaf and Hard of Hearing People.
Proceedings of the 14th Symposium on Virtual and Augmented Reality, 2012

2011
Binary Hybrid GA-PSO based algorithm for compression of hyperspectral data.
Proceedings of the 5th International Conference on Signal Processing and Communication Systems, 2011

Analyzing Area Penalty of 32-Bit Fault Tolerant ALU Using BCH Code.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Packet loss replacement in VoIP using a low-order recursive linear prediction method.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

2010
Analysis of digital DSP blocks using GDI technology.
Proceedings of the 2010 International Conference on Computer Information Systems and Industrial Management Applications, 2010

2009
The design of a low-power high-speed current comparator in 0.35-m CMOS technology.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2005
A VLSI Design Design-Synthesis Methodology at the transistor Layout Level.
Trans. SDPS, 2005

2001
Fast and accurate timing characterization using functionalinformation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

An Advanced Timing Characterization Method Using Mode Dependency.
Proceedings of the 38th Design Automation Conference, 2001

2000
A floorplanning-Synthesis Methodology for Multiple Chip Module Design.
Trans. SDPS, 2000

Transistor-Level Timing Analysis Using Embedded Simulation.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999
Functional Timing Analysis for IP Characterization.
Proceedings of the 36th Conference on Design Automation, 1999

1995
An efficient building block layout methodology for compact placement.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995


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