Mohammad Maymandi-Nejad

Orcid: 0000-0002-8592-7416

According to our database1, Mohammad Maymandi-Nejad authored at least 35 papers between 2003 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
A Variable-Capacitance Energy Harvester With Miniaturized Inductor Targeting Implantable Devices.
IEEE Trans. Ind. Electron., 2022

2020
A Low-Power Time-to-Digital Converter for Sensor Interface Circuits.
IEEE Trans. Circuits Syst., 2020

Analytical phase noise study of a back-gate coupled colpitts quadrature VCO.
Microelectron. J., 2020

Single-ended ring oscillators: analysis and design.
IET Circuits Devices Syst., 2020

2019
Design challenges for a new mostly digital VCO-based delta-sigma modulator.
IET Circuits Devices Syst., 2019

Efficient implementation of digit-serial Montgomery modular multiplier architecture.
IET Circuits Devices Syst., 2019

A Performance Comparison Between Synchronous and Asynchronous Electrostatic Harvesters.
Proceedings of the IEEE International Conference on Industrial Technology, 2019

2018
Analysis of the impact of interferers on VCO-based continuous time delta-sigma modulators.
Integr., 2018

Power Efficient Optimization Procedure for Asynchronous Electrostatic Generators.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Co-AGSA: An efficient self-adaptive approach for constrained optimization of analog IC based on the shrinking circles technique.
Integr., 2017

A new hybrid algorithm for analog ICs optimization based on the shrinking circles technique.
Integr., 2017

A new electro-static micro-generator for energy harvesting from diaphragm muscle.
Int. J. Circuit Theory Appl., 2017

An enhanced optimization kernel for analog IC design automation using the shrinking circles technique.
Eng. Appl. Artif. Intell., 2017

2016
A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Nonautoregressive Nonlinear Identification of IPMC in Large Deformation Situations Using Generalized Volterra-Based Approach.
IEEE Trans. Instrum. Meas., 2016

A low-power fast tag comparator by modifying charging scheme of wide fan-in dynamic OR gates.
Integr., 2016

2015
A Fully Digital ASK Demodulator With Digital Calibration for Bioimplantable Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Linear Comparator-Based Fully Digital Delay Element.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
Analytical model for CMOS cross-coupled LC-tank oscillator.
IET Circuits Devices Syst., 2014

2011
Ultra-low power self-calibrating process-insensitive BPSK demodulator for bio-implantable chips.
IEICE Electron. Express, 2011

Duty Cycle Shift Keying data transfer technique for bio-implantable devices.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip-Flops With Embedded Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Ultra-low power BPSK demodulator for bio-implantable chips.
IEICE Electron. Express, 2010

Capacitor scaling for low-power design of cyclic analog-to-digital converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Distortion analysis of bootstrap switch using volterra series.
IET Circuits Devices Syst., 2009

An ultra low-power low-voltage switched-comparator successive approximation analog to digital converter.
IEICE Electron. Express, 2009

An Ultra-low-power 10-Bit 100-kS/s Successive-approximation Analog-to-digital Converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A fully digital ADC using a new delay element with enhanced linearity.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 0.8-V 420nW CMOS switched-opamp switched-capacitor pacemaker front-end with a new continuous-time CMFB.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Power-Delay Efficient Overlap-Based Charge-Sharing Free Pseudo-Dynamic D Flip-Flops.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
DTMOS Technique for Low-Voltage Analog Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2006

2005
A monotonic digitally controlled delay element.
IEEE J. Solid State Circuits, 2005

A 0.8V Delta-Sigma modulator using DTMOS technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Correction to "A Digitally Programmable Delay Element: Design and Analysis".
IEEE Trans. Very Large Scale Integr. Syst., 2004

2003
A digitally programmable delay element: design and analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2003


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