Mohammad Khavari Tavana
Orcid: 0000-0002-2038-4908
According to our database1,
Mohammad Khavari Tavana
authored at least 24 papers
between 2011 and 2020.
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Bibliography
2020
Nacre<sup>*</sup>*Nacre, or mother-of-pearl, is one of nature's remarkable examples of a durable and break-resistant structure.: Durable, Secure and Energy-Efficient Non-Volatile Memory Utilizing Data Versioning.
IEEE Trans. Emerg. Top. Comput., 2020
2019
Exploiting Adaptive Data Compression to Improve Performance and Energy-Efficiency of Compute Workloads in Multi-GPU Systems.
Proceedings of the 2019 IEEE International Parallel and Distributed Processing Symposium, 2019
2018
ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Block Cooperation: Advancing Lifetime of Resistive Memories by Increasing Utilization of Error Correcting Codes.
ACM Trans. Archit. Code Optim., 2018
ACM J. Emerg. Technol. Comput. Syst., 2018
2017
Proceedings of the International Symposium on Memory Systems, 2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Exploring the Potential for Collaborative Data Compression and Hard-Error Tolerance in PCM Memories.
Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2017
Live together or Die Alone: Block cooperation to extend lifetime of resistive memories.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Two-State Checkpointing for Energy-Efficient Fault Tolerance in Hard Real-Time Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
2015
Dynamically adaptive register file architecture for energy reduction in embedded processors.
Microprocess. Microsystems, 2015
DRVS: Power-efficient reliability management through Dynamic Redundancy and Voltage Scaling under variations.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Wide I/O or LPDDR? Exploration and analysis of performance, power and temperature trade-offs of emerging DRAM technologies in embedded MPSoCs.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Adaptive Bandwidth Management for Performance-Temperature Trade-offs in Heterogeneous HMC+DDRx Memory.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling.
Proceedings of the 52nd Annual Design Automation Conference, 2015
dsReliM: Power-constrained reliability management in Dark-Silicon many-core chips under process variations.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015
2014
Simultaneous hardware and time redundancy with online task scheduling for low energy highly reliable standby-sparing system.
ACM Trans. Embed. Comput. Syst., 2014
Energy-efficient mapping of biomedical applications on domain-specific accelerator under process variation.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
Feedback-Based Energy Management in a Standby-Sparing Scheme for Hard Real-Time Systems.
Proceedings of the 32nd IEEE Real-Time Systems Symposium, 2011