Mohammad Hossein Moaiyeri
Orcid: 0000-0001-9711-7923
According to our database1,
Mohammad Hossein Moaiyeri
authored at least 76 papers
between 2008 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
A new method for securing binary deep neural networks against model replication attacks using magnetic tunnel junctions.
Int. J. Inf. Sec., February, 2025
Balancing precision and efficiency: an approximate multiplier with built-in error compensation for error-resilient applications.
J. Supercomput., January, 2025
2024
A New Paradigm for Immunization of Deep Neural Networks Against Replication Attacks Based on Spintronics.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2024
Protecting the Intellectual Property of Binary Deep Neural Networks With Efficient Spintronic-Based Hardware Obfuscation.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2024
IEEE Trans. Fuzzy Syst., May, 2024
A Reconfigurable Nonvolatile Memory Architecture for Prolonged Wearable Health Monitoring Devices.
IEEE Trans. Consumer Electron., May, 2024
On the Layout-Oriented Investigation of Power Attack Hardness of Spintronic-Based Logic Circuits.
Circuits Syst. Signal Process., May, 2024
Circuits Syst. Signal Process., February, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
2023
Ultra-efficient fully programmable membership function generator based on independent double-gate FinFET technology.
Int. J. Circuit Theory Appl., October, 2023
A look-up table-based processing-in-SRAM architecture for energy-efficient search applications.
Comput. Electr. Eng., September, 2023
IET Circuits Devices Syst., July, 2023
J. Signal Process. Syst., April, 2023
An Ultra-Efficient Approximate Multiplier With Error Compensation for Error-Resilient Applications.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
Hardware-accuracy trade-offs for error-resilient applications using an ultra-efficient hybrid approximate multiplier.
J. Supercomput., 2023
High-Performance and Robust Spintronic/CNTFET-Based Binarized Neural Network Hardware Accelerator.
IEEE Trans. Emerg. Top. Comput., 2023
A Flexible and Reliable RRAM-Based In-Memory Computing Architecture for Data-Intensive Applications.
IEEE Trans. Emerg. Top. Comput., 2023
A Hybrid SRAM/RRAM In-Memory Computing Architecture Based on a Reconfigurable SRAM Sense Amplifier.
IEEE Access, 2023
2022
Nonvolatile Associative Memory Design Based on Spintronic Synapses and CNTFET Neurons.
IEEE Trans. Emerg. Top. Comput., 2022
Energy- and Quality-Efficient Approximate Multipliers for Neural Network and Image Processing Applications.
IEEE Trans. Emerg. Top. Comput., 2022
Correction to "Leveraging Negative Capacitance CNTFETs for Image Processing: An Ultra-Efficient Ternary Image Edge Detection Hardware".
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A process variation resilient spintronic true random number generator for highly reliable hardware security applications.
Microelectron. J., 2022
A Hardware- and Accuracy-Efficient Approximate Multiplier with Error Compensation for Neural Network and Image Processing Applications.
Circuits Syst. Signal Process., 2022
A Reliable and Energy-Efficient Nonvolatile Ternary Memory Based on Hybrid FinFET/RRAM Technology.
IEEE Access, 2022
2021
High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Ultra-Compact Ternary Logic Gates Based on Negative Capacitance Carbon Nanotube FETs.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Leveraging Negative Capacitance CNTFETs for Image Processing: An Ultra-Efficient Ternary Image Edge Detection Hardware.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic.
Microelectron. J., 2021
Ultraefficient imprecise multipliers based on innovative 4: 2 approximate compressors.
Int. J. Circuit Theory Appl., 2021
Ultra-Compact Imprecise 4: 2 Compressor and Multiplier Circuits for Approximate Computing in Deep Nanoscale.
Circuits Syst. Signal Process., 2021
Ultra-High-Performance Magnetic Nonvolatile Level Converter Flip-Flop with Spin-Hall Assistance for Dual-Supply Systems with Power Gating Architecture.
Circuits Syst. Signal Process., 2021
Breaking the Limits in Ternary Logic: An Ultra-Efficient Auto-Backup/Restore Nonvolatile Ternary Flip-Flop Using Negative Capacitance CNTFET Technology.
IEEE Access, 2021
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021
Proceedings of the 26th International Computer Conference, Computer Society of Iran, 2021
2020
Design of an efficient fully nonvolatile and radiation-hardened majority-based magnetic full adder using FinFET/MTJ.
Microelectron. J., 2020
NVLCFF: An Energy-Efficient Magnetic Nonvolatile Level Converter Flip-Flop for Ultra-Low-Power Design.
Circuits Syst. Signal Process., 2020
A novel digital fuzzy system for image edge detection based on wrap-gate carbon nanotube transistors.
Comput. Electr. Eng., 2020
Low-Cost Implementation of Bilinear and Bicubic Image Interpolation for Real-Time Image Super-Resolution.
Proceedings of the IEEE Global Humanitarian Technology Conference, 2020
2019
Comparative Analysis of Simultaneous Switching Noise Effects in MWCNT Bundle and Cu Power Interconnects in CNTFET-Based Ternary Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A Majority-Based Imprecise Multiplier for Ultra-Efficient Approximate Image Multiplication.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
IEEE Trans. Fuzzy Syst., 2018
An Energy- and Area-Efficient Approximate Ternary Adder Based on CNTFET Switching Logic.
Circuits Syst. Signal Process., 2018
2017
Microprocess. Microsystems, 2017
2016
CNFET-based approximate ternary adders for energy-efficient image processing applications.
Microprocess. Microsystems, 2016
Frontiers Inf. Technol. Electron. Eng., 2016
J. Low Power Electron., 2016
Circuits Syst. Signal Process., 2016
2015
Microelectron. J., 2015
Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach.
Microelectron. J., 2015
Microprocess. Microsystems, 2015
J. Circuits Syst. Comput., 2015
Int. J. High Perform. Syst. Archit., 2015
2013
A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits.
IET Comput. Digit. Tech., 2013
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
2012
IEICE Trans. Electron., 2012
IEICE Electron. Express, 2012
Circuits Syst. Signal Process., 2012
Circuits Syst. Signal Process., 2012
2011
Design and implementation of Multistage Interconnection Networks using Quantum-dot Cellular Automata.
Microelectron. J., 2011
J. Circuits Syst. Comput., 2011
Integr., 2011
IET Circuits Devices Syst., 2011
A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders.
Fuzzy Sets Syst., 2011
Proceedings of the 19th International Euromicro Conference on Parallel, 2011
Comparative Performance Study of Multi-stage Interconnection Networks Using Carbon Nanotube Switches.
Proceedings of the IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, 2011
2009
2008