Mohammad Hossein Hajkazemi

According to our database, Mohammad Hossein Hajkazemi authored at least 21 papers between 2013 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Beating the I/O bottleneck: a case for log-structured virtual disks.

Mohammad Hossein Hajkazemi, Vojtech Aschenbrenner, Mania Abdi, Emine Ugur Kaynar, Amin Mossayebzadeh, Orran Krieger, Peter Desnoyers

Proceedings of the EuroSys '22: Seventeenth European Conference on Computer Systems, Rennes, France, April 5, 2022

2021

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Mania Abdi, Amin Mosayyebzadeh, Mohammad Hossein Hajkazemi, Emine Ugur Kaynar, Ata Turk, Larry Rudolph, Orran Krieger, Peter Desnoyers

Proceedings of the 19th USENIX Conference on File and Storage Technologies, 2021

2020

μCache: a mutable cache for SMR translation layer.

Mohammad Hossein Hajkazemi, Mania Abdi, Peter Desnoyers

Proceedings of the 28th International Symposium on Modeling, 2020

2019

Track-based Translation Layers for Interlaced Magnetic Recording.

Mohammad Hossein Hajkazemi, Ajay Narayan Kulkarni, Peter Desnoyers, Timothy R. Feldman

Proceedings of the 2019 USENIX Annual Technical Conference, 2019

Caching in the Multiverse.

Mania Abdi, Amin Mosayyebzadeh, Mohammad Hossein Hajkazemi, Ata Turk, Orran Krieger, Peter Desnoyers

Proceedings of the 11th USENIX Workshop on Hot Topics in Storage and File Systems, 2019

D3N: A multi-layer cache for the rest of us.

Emine Ugur Kaynar, Mania Abdi, Mohammad Hossein Hajkazemi, Ata Turk, Raja R. Sambasivan, David Cohen, Larry Rudolph, Peter Desnoyers, Orran Krieger

Proceedings of the 2019 IEEE International Conference on Big Data (IEEE BigData), 2019

2018

ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling.

Mohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Divya Pathak, Ioannis Savidis, Houman Homayoun

IEEE Trans. Very Large Scale Integr. Syst., 2018

Heterogeneous HMC+DDRx Memory Management for Performance-Temperature Tradeoffs.

Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Tinoosh Mohsenin, Houman Homayoun

ACM J. Emerg. Technol. Comput. Syst., 2018

FSTL: A Framework to Design and Explore Shingled Magnetic Recording Translation Layers.

Mohammad Hossein Hajkazemi, Mania Abdi, Mansour Shafaei, Peter Desnoyers

Proceedings of the 26th IEEE International Symposium on Modeling, 2018

Minimizing Read Seeks for SMR Disk.

Mohammad Hossein Hajkazemi, Mania Abdi, Peter Desnoyers

Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018

2017

Modeling Drive-Managed SMR Performance.

Mansour Shafaei, Mohammad Hossein Hajkazemi, Peter Desnoyers, Abutalib Aghayev

ACM Trans. Storage, 2017

2016

Modeling SMR Drive Performance.

Mansour Shafaei, Mohammad Hossein Hajkazemi, Peter Desnoyers, Abutalib Aghayev

Proceedings of the 2016 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Science, 2016

Energy efficient on-chip power delivery with run-time voltage regulator clustering.

Divya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Houman Homayoun, Ioannis Savidis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Load Balanced On-Chip Power Delivery for Average Current Demand.

Divya Pathak, Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Houman Homayoun, Ioannis Savidis

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015

Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping.

Mohammad Khavari Tavana, Divya Pathak, Mohammad Hossein Hajkazemi, Maria Malik, Ioannis Savidis, Houman Homayoun

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Wide I/O or LPDDR? Exploration and analysis of performance, power and temperature trade-offs of emerging DRAM technologies in embedded MPSoCs.

Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Houman Homayoun

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Adaptive Bandwidth Management for Performance-Temperature Trade-offs in Heterogeneous HMC+DDRx Memory.

Mohammad Hossein Hajkazemi, Michael Chorney, Reyhaneh Jabbarvand Behrouz, Mohammad Khavari Tavana, Houman Homayoun

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling.

Mohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Divya Pathak, Ioannis Savidis, Houman Homayoun

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

An Alternative Hybrid Power-Aware Adder for High-Performance Processors.

Mohammad Hossein Hajkazemi, Amirali Baniasadi

J. Low Power Electron., 2014

Enabling Dynamic Heterogeneity Through Core-on-Core Stacking.

Vasileios Kontorinis, Mohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Dean M. Tullsen, Houman Homayoun

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

FARHAD: A Fault-Tolerant Power-Aware Hybrid Adder for add intensive applications.

Mohammad Hossein Hajkazemi, Amirali Baniasadi, Hossein Asadi

Proceedings of the 24th International Conference on Application-Specific Systems, 2013