Mohammad H. Naderi

According to our database, Mohammad H. Naderi authored at least 4 papers between 2017 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers.

Mohammad H. Naderi, Chulhyun Park, Suraj Prakash, Martin Kinyua, Eric G. Soenen, José Silva-Martínez

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018

Operational Transconductance Amplifier With Class-B Slew-Rate Boosting for Fast High-Performance Switched-Capacitor Circuits.

Mohammad H. Naderi, Suraj Prakash, José Silva-Martínez

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Low noise RF quadrature VCO using tail-switch network-based coupling in 40 nm CMOS.

Venkatraman Natarajan, Mohammad H. Naderi, José Silva-Martínez

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017

Algorithmic-pipelined ADC with a modified residue curve for better linearity.

Mohammad H. Naderi, José Silva-Martínez

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017