Mohammad Gholami

Orcid: 0000-0001-8275-3230

According to our database1, Mohammad Gholami authored at least 64 papers between 2010 and 2024.

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Bibliography

2024
Four-Cycle Free Spatially Coupled LDPC Codes With an Explicit Construction.
IEEE Commun. Lett., July, 2024

On a class of column-weight 3 decomposable LDPC codes with the analysis of elementary trapping sets.
IET Commun., June, 2024

2023
Low-power, high-speed, and area-efficient sequential circuits by quantum-dot cellular automata: T-latch and counter study.
Frontiers Inf. Technol. Electron. Eng., March, 2023

A Two-Stage Flexibility-Oriented Stochastic Energy Management Strategy for Multi-Microgrids Considering Interaction With Gas Grid.
IEEE Trans. Engineering Management, 2023

A general jitter analysis of DLL considering the jitter accumulation effect of loop capacitor.
Microprocess. Microsystems, 2023

Design of a Novel Decimal to Multicode Converter in QCA Technology.
J. Electr. Comput. Eng., 2023

4-Cycle Free Spatially Coupled LDPC Codes with an Explicit Construction.
CoRR, 2023

An Efficient Algorithm for Counting Cycles in QC and APM LDPC Codes.
CoRR, 2023

Developing an Optimal Framework for PMU Placement Based on Active Distribution System State Estimation Considering Cost-Worth Analysis.
IEEE Access, 2023

2022
Selective counter design in quantum-dot cellular automata nanotechnology.
Concurr. Comput. Pract. Exp., 2022

Latch and flip-flop design in QCA technology with minimum number of cells.
Comput. Electr. Eng., 2022

A Novel Distributed Paradigm for Energy Scheduling of Islanded Multiagent Microgrids.
IEEE Access, 2022

2021
A low power and jitter delay cell with pulse width modulation for wide range delay lock loops.
Microelectron. J., 2021

Analysis and design of a low jitter delay-locked loop using lock state detector.
Int. J. Circuit Theory Appl., 2021

Novel quantum-dot cellular automata implementation of flip-flop and phase-frequency detector based on nand-nor-inverter gates.
Int. J. Circuit Theory Appl., 2021

On the Construction of Multitype Quasi-Cyclic Low-Density Parity-Check Codes With Different Girth and Length.
IEEE Access, 2021

Determining the Optimum Network Division Scheme for Multi-area Distribution System State Estimation.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Europe, 2021

Management of Flexible Resources for Voltage Regulation of Distribution Systems.
Proceedings of the IEEE PES Innovative Smart Grid Technologies Europe, 2021

2020
Detecting the Location of Short-Circuit Faults in Active Distribution Network Using PMU-Based State Estimation.
IEEE Trans. Smart Grid, 2020

On the Class of High-Rate QC-LDPC Codes With Girth 8 From Sequences Satisfied in GCD Condition.
IEEE Commun. Lett., 2020

A Low-Power and High-Frequency Phase Frequency Detector for a 3.33-GHz Delay Locked Loop.
Circuits Syst. Signal Process., 2020

2019
An ad hoc distributed systems approach for industrial wireless sensor network management.
J. Ind. Inf. Integr., 2019

LDPC codes based on Mobius transformations.
IET Commun., 2019

Low-Power High-Frequency Phase Frequency Detector for Minimal Blind-Zone Phase-Locked Loops.
Circuits Syst. Signal Process., 2019

Two Novel Ultra-Low-Power SRAM Cells with Separate Read and Write Path.
Circuits Syst. Signal Process., 2019

4-Bit serial shift register with reset ability and 4-bit LFSR in QCA technology using minimum number of cells and delay.
Comput. Electr. Eng., 2019

Design of novel D flip-flops with set and reset abilities in quantum-dot cellular automata nanotechnology.
Comput. Electr. Eng., 2019

2018
A novel rising Edge Triggered Resettable D flip-flop using five input majority gate.
Microprocess. Microsystems, 2018

Low-power and wide-band delay-locked loop with switching delay line.
Int. J. Circuit Theory Appl., 2018

Design and analysis of high linearity mixer using subharmonic technique.
Int. J. Circuit Theory Appl., 2018

A wide range delay locked loop for low power and low jitter applications.
Int. J. Circuit Theory Appl., 2018

Anti Quasi-Cyclic LDPC Codes.
IEEE Commun. Lett., 2018

2017
Explicit APM-LDPC Codes With Girths 6, 8, and 10.
IEEE Signal Process. Lett., 2017

Design of 3.1 to 10.6 GHz ultra-wideband flat gain LNA.
Int. J. Circuit Theory Appl., 2017

Using a memristor crossbar structure to implement a novel adaptive real-time fuzzy modeling algorithm.
Fuzzy Sets Syst., 2017

Phase Detector with Minimal Blind Zone and Reset Time for GSamples/s DLLs.
Circuits Syst. Signal Process., 2017

A Novel Charge Pump with Low Current for Low-Power Delay-Locked Loops.
Circuits Syst. Signal Process., 2017

2016
Total Jitter of Delay-Locked Loops Due to Four Main Jitter Sources.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Comparison of Alternative Distributed Dynamic Cluster Formation Techniques for Industrial Wireless Sensor Networks.
Sensors, 2016

Analysis of frequency and amplitude in CMOS differential ring oscillators.
Integr., 2016

Row and Column Extensions of 4-Cycle Free LDPC Codes.
IEEE Commun. Lett., 2016

2015
A new fast-lock, low-jitter, and all-digital frequency synthesizer for DVB-T receivers.
Int. J. Circuit Theory Appl., 2015

High-performance binary and non-binary Low-density parity-check codes based on affine permutation matrices.
IET Commun., 2015

2014
Distributed autonomous systems to track mobile nodes in industrial wireless sensor networks.
PhD thesis, 2014

Jitter of Delay-Locked Loops Due to PFD.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Quasi-cyclic low-density parity-check codes based on finite set systems.
IET Commun., 2014

Digital delay locked loop-based frequency synthesiser for Digital Video Broadcasting-Terrestrial receivers.
IET Circuits Devices Syst., 2014

Large Girth Column-Weight Two and Three LDPC Codes.
IEEE Commun. Lett., 2014

Design of Novel Testable and Diagnosable Phase-Frequency Detector.
Circuits Syst. Signal Process., 2014

Double Cylinder Cycle codes of Arbitrary Girth.
CoRR, 2014

Quasi Cyclic LDPC Codes Based on Finite Set Systems.
CoRR, 2014

Column Weight Two and Three LDPC Codes with High Rates and Large Girths.
CoRR, 2014

Comparing alternative cluster management approaches for mobile node tracking in a factory Wireless Sensor Network.
Proceedings of the 2014 IEEE International Conference on Systems, Man, and Cybernetics, 2014

2013
Column-Weight Three QC LDPC Codes with Girth 20.
IEEE Commun. Lett., 2013

Design of Binary and Nonbinary Codes from Lifting of Girth-8 Cycle Codes with Minimum Lengths.
IEEE Commun. Lett., 2013

Analysis of DLL Jitter due to Voltage-Controlled Delay Line.
Circuits Syst. Signal Process., 2013

A Novel Low Power Architecture for DLL-Based Frequency Synthesizers.
Circuits Syst. Signal Process., 2013

Dynamic Cluster Formation and Management in a Factory Wireless Sensor Network.
Proceedings of the IEEE International Conference on Systems, 2013

2012
Application-Oriented Intelligent Middleware for Distributed Sensing and Control.
IEEE Trans. Syst. Man Cybern. Part C, 2012

Evaluating alternative approaches to mobile object localization in wireless sensor networks with passive architecture.
Comput. Ind., 2012

2011
A novel architecture for low voltage-low power DLL-based frequency multipliers.
IEICE Electron. Express, 2011

A low power 1-V 10-bit 40-MS/s pipeline ADC.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Localization of Industrial Wireless Sensor Networks: An Artificial Neural Network Approach.
Proceedings of the Holonic and Multi-Agent Systems for Manufacturing, 2011

2010
Modeling of DLL-based frequency multiplier in time and frequency domain with Matlab Simulink.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010


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