Mohammad Arjomand
Orcid: 0000-0003-1213-7349
According to our database1,
Mohammad Arjomand
authored at least 49 papers
between 2008 and 2018.
Collaborative distances:
Collaborative distances:
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On csauthors.net:
Bibliography
2018
IEEE Trans. Computers, 2018
Chapter Two - Revisiting Processor Allocation and Application Mapping in Future CMPs in Dark Silicon Era.
Adv. Comput., 2018
Proceedings of the 26th IEEE International Symposium on Modeling, 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
2017
IEEE Trans. Parallel Distributed Syst., 2017
Efficient Mapping of Applications for Future Chip-Multiprocessors in Dark Silicon Era.
ACM Trans. Design Autom. Electr. Syst., 2017
Exploiting Data Longevity for Enhancing the Lifetime of Flash-based Storage Class Memory.
Proc. ACM Meas. Anal. Comput. Syst., 2017
Proceedings of the 25th High Performance Computing Symposium, Virginia Beach, VA, USA, April 23, 2017
A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core Systems.
Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, Urbana-Champaign, IL, USA, June 05, 2017
Proceedings of the International Symposium on Memory Systems, 2017
Exploring the impact of memory block permutation on performance of a crossbar ReRAM main memory.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017
Leveraging value locality for efficient design of a hybrid cache in multicore processors.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Exploring the Potential for Collaborative Data Compression and Hard-Error Tolerance in PCM Memories.
Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2017
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2016
A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I/O Characterization.
IEEE Trans. Computers, 2016
Exploring the potentials of parallel garbage collection in SSDs for enterprise storage systems.
Proceedings of the International Conference for High Performance Computing, 2016
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016
Efficient processor allocation in a reconfigurable CMP architecture for dark silicon era.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
ACM Trans. Design Autom. Electr. Syst., 2015
ACM Trans. Design Autom. Electr. Syst., 2015
Evaluating the Combined Impact of Node Architecture and Cloud Workload Characteristics on Network Traffic and Performance/Cost.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015
2014
A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure.
Comput. Electr. Eng., 2014
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014
2013
Efficient genetic based topological mapping using analytical models for on-chip networks.
J. Comput. Syst. Sci., 2013
Network-on-SSD: A Scalable and High-Performance Communication Design Paradigm for SSDs.
IEEE Comput. Archit. Lett., 2013
2011
Proceedings of the 19th International Euromicro Conference on Parallel, 2011
High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
2010
Power-Performance Analysis of Networks-on-Chip With Arbitrary Buffer Allocation Schemes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
2009
Proceedings of the 23rd international conference on Supercomputing, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the IEEE 23rd International Conference on Advanced Information Networking and Applications, 2009
2008
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008