Mohammad A. Ahmed

IEEE Trans. Very Large Scale Integr. Syst., 2019

2016

Performance optimization and power efficiency in 3D IC with buffer insertion scheme.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Buffered Interconnects in 3D IC Layout Design.

[BibT_eX]

[DOI]

Proceedings of the 18th System Level Interconnect Prediction Workshop, 2016

2015

Dynamic nets-to-TSVs assignment in 3D floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

TSVs in early layout design exploration for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Delay and power optimization with TSV-aware 3D floorplanning.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes.

[BibT_eX]

[DOI]

Muhammad Ali

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

3D floorplanning with nets-to-TSVs assignment.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013

TSV capacitance aware 3-D floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

TSV stress-aware performance and reliability analysis.

[BibT_eX]

[DOI]

Muhammad Ali

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Fast floorplanning for fixed-outline and nonrectangular regions.

[BibT_eX]

[DOI]

Shantesh Pinge