Mohamed Megahed

According to our database, Mohamed Megahed authored at least 12 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation.

Mohamed Megahed, Yusang Chun, Zhiping Wang, Tejasvi Anand

IEEE J. Solid State Circuits, August, 2024

2023

A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS.

Mohamed Megahed, Tejasvi Anand

IEEE J. Solid State Circuits, May, 2023

Weight Prediction Using the Hybrid Stacked-LSTM Food Selection Model.

Ahmed M. Elshewey, Mahmoud Y. Shams, Zahraa Tarek, Mohamed Megahed, El-Sayed M. El-Kenawy, Mohamed A. El-dosuky

Comput. Syst. Sci. Eng., 2023

2022

A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS.

Yusang Chun, Mohamed Megahed, Ashwin Ramachandran, Tejasvi Anand

IEEE J. Solid State Circuits, 2022

A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail.

Xiaohui Lin, Mohamed Megahed, Tejasvi Anand

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

A Machine Learning Inspired Transceiver with ISI-Resilient Data Encoding: Hybrid-Ternary Coding + 2-Tap FFE + CTLE + Feature Extraction and Classification for 44.7dB Channel Loss in 7.3pJ/bit.

Zhiping Wang, Mohamed Megahed, Yusang Chun, Tejasvi Anand

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A 27 Gb/s 5.39 pJ/bit 8-ary Modulated Wireline Transceiver Using Pulse Width and Amplitude Modulation Achieving 9.5 dB SNR Improvement over PAM-8.

Mohamed Megahed, Yusang Chun, Zhiping Wang, Tejasvi Anand

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020

An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS.

Ashwin Ramachandran, Yusang Chun, Mohamed Megahed, Tejasvi Anand

IEEE J. Solid State Circuits, 2020

2019

A Switched Capacitor Multiple Input Single Output Energy Harvester (Solar + Piezo) Achieving 74.6% Efficiency With Simultaneous MPPT.

Abhishekh Devaraj, Mohamed Megahed, Yutao Liu, Ashwin Ramachandran, Tejasvi Anand

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Sub 1μW Switched Source + Capacitor Architecture Free of Top/Bottom Plate Parasitic Switching Loss Achieving Peak Efficiency of 80.66% at a Regulated 1.8V Output in 180nm.

Mohamed Megahed, Y. Ramadass, Tejasvi Anand

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2017

FA*IR: A Fair Top-k Ranking Algorithm.

Meike Zehlike, Francesco Bonchi, Carlos Castillo, Sara Hajian, Mohamed Megahed, Ricardo Baeza-Yates

Proceedings of the 2017 ACM on Conference on Information and Knowledge Management, 2017

2016

12-Gb/s low-power voltage-mode driver for multi-standard serial-link applications.

Mohamed Megahed, Mohamed R. M. Rizk, Sameh A. Ibrahim, Mohamed Dessouky

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016