Mohamed Khalil Hani

Orcid: 0000-0002-2375-5719

According to our database1, Mohamed Khalil Hani authored at least 38 papers between 2002 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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On csauthors.net:

Bibliography

2022
Accurate and compact convolutional neural network based on stochastic computing.
Neurocomputing, 2022

2021
Low-area and accurate inner product and digital filters based on stochastic computing.
Signal Process., 2021

2019
Spectral-based convolutional neural network without multiple spatial-frequency domain switchings.
Neurocomputing, 2019

Accurate and compact stochastic computations by exploiting correlation.
Turkish J. Electr. Eng. Comput. Sci., 2019

2018
Improved quantum circuit modelling based on Heisenberg representation.
Quantum Inf. Process., 2018

Optimizing FPGA-based CNN accelerator for energy efficiency with an extended Roofline model.
Turkish J. Electr. Eng. Comput. Sci., 2018

Paroxysmal atrial fibrillation prediction based on HRV analysis and non-dominated sorting genetic algorithm III.
Comput. Methods Programs Biomed., 2018

2017
A real-time near infrared image acquisition system based on image quality assessment.
J. Real Time Image Process., 2017

An optimized buffer insertion algorithm with delay-power constraints for VLSI layouts.
Turkish J. Electr. Eng. Comput. Sci., 2017

2016
An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture.
Int. J. Reconfigurable Comput., 2016

Bounded activation functions for enhanced training stability of deep neural networks on visual pattern recognition problems.
Neurocomputing, 2016

An optimized second order stochastic learning algorithm for neural network training.
Neurocomputing, 2016

Paroxysmal atrial fibrillation prediction method with shorter HRV sequences.
Comput. Methods Programs Biomed., 2016

Distributed B-SDLM: Accelerating the Training Convergence of Deep Neural Networks Through Parallelism.
Proceedings of the PRICAI 2016: Trends in Artificial Intelligence, 2016

2015
Convolutional Neural Networks with Fused Layers Applied to Face Recognition.
Int. J. Comput. Intell. Appl., 2015

OpenCL-based hardware-software co-design methodology for image processing implementation on heterogeneous FPGA platform.
Proceedings of the 2015 IEEE International Conference on Control System, 2015

Sleep Apnea Event Detection System Based on Heart Rate Variability Analysis.
Proceedings of the Second International Conference on Advanced Data and Information Engineering, 2015

Paroxysmal Atrial Fibrillation Onset Prediction Using Heart Rate Variability Analysis and Genetic Algorithm for Optimization.
Proceedings of the Second International Conference on Advanced Data and Information Engineering, 2015

2014
Hardware implementation of evolvable block-based neural networks utilizing a cost efficient sigmoid-like activation function.
Neurocomputing, 2014

Optimization of structure and system latency in evolvable block-based neural networks using genetic algorithm.
Neurocomputing, 2014

An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

FPGA-based quantum circuit emulation: A case study on Quantum Fourier transform.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A convolutional neural network approach for face verification.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

2013
Biometric encryption based on a fuzzy vault scheme with a fast chaff generation algorithm.
Future Gener. Comput. Syst., 2013

HW/SW co-design of reconfigurable hardware-based genetic algorithm in FPGAs applicable to a variety of problems.
Computing, 2013

FPGA embedded hardware system for finger vein biometric recognition.
Proceedings of the IECON 2013, 2013

Co-simulation methodology for improved design and verification of hardware neural networks.
Proceedings of the IECON 2013, 2013

2012
Parameterizable Decision Tree Classifier on NetFPGA.
Proceedings of the Intelligent Informatics, 2012

GA-based parameter tuning in finger-vein biometric embedded systems for information security.
Proceedings of the 2012 1st IEEE International Conference on Communications in China (ICCC), 2012

2011
Character Recognition of License Plate Number Using Convolutional Neural Network.
Proceedings of the Visual Informatics: Sustaining Research and Innovations, 2011

A Network-on-Chip simulation framework for homogeneous Multi-Processor System-on-Chip.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Securing cryptographic key with fuzzy vault based on a new chaff generation method.
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010

A Particle Swarm Optimization Approach for Routing in VLSI.
Proceedings of the Second International Conference on Computational Intelligence, 2010

2009
Accelerating the AES encryption function in OpenSSL for embedded systems.
Int. J. Inf. Commun. Technol., 2009

SystemC-based HW/SW co-simulation platform for system-on-chip (SoC) design space exploration.
Int. J. Inf. Commun. Technol., 2009

A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography.
Int. J. Inf. Commun. Technol., 2009

Modeling of a Ladder Logic Processor for High Performance Prgrammable Logic Controller.
Proceedings of the Third Asia International Conference on Modelling & Simulation, 2009

2002
Implementation of Recurrent Neural Network Algorithm for Shortest Path Calculation in Network Routing.
Proceedings of the International Symposium on Parallel Architectures, 2002


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