Mohamed Hassan

Orcid: 0000-0001-5926-5861

Affiliations:
  • McMaster University, Department of Electrical and Computer Engineering, Hamilton, ON, Canad
  • Intel Corporation, Intel PSG, Toronto, ON, Canada
  • University of Guelph, ON, Canada
  • University of Waterloo, Waterloo, ON, Canada (PhD 2017)


According to our database1, Mohamed Hassan authored at least 39 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
HW/SW Collaborative Techniques for Accelerating TinyML Inference Time at No Cost.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

Event Monitor Validation in High-Integrity Systems.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

Shared Data Kills Real-Time Cache Analysis. How to Resurrect It?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
DISCO: Time-Compositional Cache Coherence for Multi-Core Real-Time Embedded Systems.
IEEE Trans. Computers, April, 2023

PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems.
ACM Trans. Embed. Comput. Syst., 2023

The Case for tinyML in Healthcare: CNNs for Real-Time On-Edge Blood Pressure Estimation.
Proceedings of the 38th ACM/SIGAPP Symposium on Applied Computing, 2023

Tracking Coherence-Related Contention Delays in Real-Time Multicore Systems.
Proceedings of the 38th ACM/SIGAPP Symposium on Applied Computing, 2023

Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems.
Proceedings of the IEEE Real-Time Systems Symposium, 2023

A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources.
Proceedings of the 35th Euromicro Conference on Real-Time Systems, 2023

2022
tinyCare: A tinyML-based Low-Cost Continuous Blood Pressure Estimation on the Extreme Edge.
Proceedings of the 10th IEEE International Conference on Healthcare Informatics, 2022

Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds.
Proceedings of the 34th Euromicro Conference on Real-Time Systems, 2022

Predictably and Efficiently Integrating COTS Cache Coherence in Real-Time Systems.
Proceedings of the 34th Euromicro Conference on Real-Time Systems, 2022

2021
Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems.
IEEE Trans. Computers, 2021

DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance.
Proceedings of the MEMSYS 2021: The International Symposium on Memory Systems, Washington, USA, September 27, 2021

Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache Coherence.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Duetto: Latency Guarantees at Minimal Performance Cost.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Reduced latency DRAM for multi-core safety-critical real-time systems.
Real Time Syst., 2020

MCsim: An Extensible DRAM Memory Controller Simulator.
IEEE Comput. Archit. Lett., 2020

The Best of All Worlds: Improving Predictability at the Performance of Conventional Coherence with No Protocol Modifications.
Proceedings of the 41st IEEE Real-Time Systems Symposium, 2020

DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining.
Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, 2020

Analysis of Memory-Contention in Heterogeneous COTS MPSoCs.
Proceedings of the 32nd Euromicro Conference on Real-Time Systems, 2020

Discriminative Coherence: Balancing Performance and Latency Bounds in Data-Sharing Multi-Core Real-Time Systems.
Proceedings of the 32nd Euromicro Conference on Real-Time Systems, 2020

2019
Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems.
Proceedings of the IEEE Real-Time Systems Symposium, 2019

Managing DRAM Interference in Mixed Criticality Embedded Systems.
Proceedings of the 31st International Conference on Microelectronics, 2019

2018
Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis.
ACM Trans. Embed. Comput. Syst., 2018

A Comparative Study of Predictable DRAM Controllers.
ACM Trans. Embed. Comput. Syst., 2018

Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

MCXplore: Automating the Validation Process of DRAM Memory Controller Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Heterogeneous MPSoCs for Mixed-Criticality Systems: Challenges and Opportunities.
IEEE Des. Test, 2018

On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?
Proceedings of the 2018 IEEE Real-Time Systems Symposium, 2018

2017
Predictable Shared Memory Resources for Multi-Core Real-Time Systems.
PhD thesis, 2017

PMC: A Requirement-Aware DRAM Controller for Multicore Mixed Criticality Systems.
ACM Trans. Embed. Comput. Syst., 2017

HourGlass: Predictable Time-based Cache Coherence Protocol for Dual-Critical Multi-Core Systems.
CoRR, 2017

Predictable Cache Coherence for Multi-core Real-Time Systems.
Proceedings of the 2017 IEEE Real-Time and Embedded Technology and Applications Symposium, 2017

2016
Criticality- and Requirement-Aware Bus Arbitration for Multi-Core Mixed Criticality Systems.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

MCXplore: An automated framework for validating memory controller designs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems.
Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015

Reverse-engineering embedded memory controllers through latency-based analysis.
Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015


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