Mohamed Eldafrawy

Orcid: 0000-0002-4157-8584

According to our database¹, Mohamed Eldafrawy authored at least 4 papers between 2017 and 2020.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

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2020

VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling.

[BibT_eX]

[DOI]

Jean-Philippe Legault

ACM Trans. Reconfigurable Technol. Syst., 2020

FPGA Logic Block Architectures for Efficient Deep Learning Inference.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2020

2019

Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2017

An event-based Network-on-Chip debugging system for FPGA-based MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Mohamed Eldafrawy

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