Moaz Mostafa

Orcid: 0000-0001-7052-625X

According to our database1, Moaz Mostafa authored at least 4 papers between 2014 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2021
A Novel Flow for Reducing Dynamic Power and Conditional Performance Improvement.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2019
A Dynamic Power Reduction Methodology based on Reducing Output Transition Rate.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2019

2015
SystemVerilog assertion debugging: A visualization and pattern matching model.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015

2014
System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation.
Proceedings of the 15th International Microprocessor Test and Verification Workshop, 2014


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