Mitsuyuki Watanabe
According to our database1,
Mitsuyuki Watanabe
authored at least 11 papers
between 2008 and 2021.
Collaborative distances:
Collaborative distances:
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Bibliography
2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2019
A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2013
A 19 nm 112.8 mm<sup>2</sup> 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface.
IEEE J. Solid State Circuits, 2013
2012
IEEE J. Solid State Circuits, 2012
A 19nm 112.8mm<sup>2</sup> 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2009
A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008