Mitsuyasu Ohta

According to our database, Mitsuyasu Ohta authored at least 7 papers between 1995 and 2002.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2002

A Test Point Insertion Method to Reduce the Number of Test Patterns.

Masayoshi Yoshimura, Toshinori Hosokawa, Mitsuyasu Ohta

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

A New Inter-Core Built-In-Self-Test Circuits for Tri-State Buffers in the System on a Chip.

Tetsuji Kishi, Mitsuyasu Ohta, Takashi Taniguchi, Hiroshi Kadota

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times.

Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta

Proceedings of ASP-DAC 2001, 2001

2000

On validating data hold times for flip-flops in sequential circuits.

Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1997

A Partial Scan Design Method Based on n-Fold Line-up Structures.

Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

A Design for testability Method Using RTL Partitioning.

Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Design for testability using register-transfer level partial scan selection.

Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995