Mitsutaka Niiro

According to our database1, Mitsutaka Niiro authored at least 7 papers between 1991 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2005
A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications.
IEEE J. Solid State Circuits, 2005

2002
0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability.
IEEE J. Solid State Circuits, 2002

A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications.
IEEE J. Solid State Circuits, 2001

A shared built-in self-repair analysis for multiple embedded memories.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
A built-in self-repair analyzer (CRESTA) for embedded DRAMs.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1991
Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyond.
IEEE J. Solid State Circuits, November, 1991


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