Mitsuru Shiozaki
Orcid: 0000-0003-3217-5262
According to our database1,
Mitsuru Shiozaki
authored at least 29 papers
between 2005 and 2023.
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Bibliography
2023
Exploring Effect of Residual Electric Charges on Cryptographic Circuits: Extended Version.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023
2021
Microprocess. Microsystems, November, 2021
Simple electromagnetic analysis attack based on geometric leak on ASIC implementation of ring-oscillator PUF.
J. Cryptogr. Eng., 2021
Model Reverse-Engineering Attack against Systolic-Array-Based DNN Accelerator Using Correlation Power Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
2020
IACR Cryptol. ePrint Arch., 2020
Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2020
2019
Model-Extraction Attack Against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019
Simple Electromagnetic Analysis Attacks based on Geometric Leak on an ASIC Implementation of Ring-Oscillator PUF.
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019
2018
Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018
2017
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017
2015
Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
J. Cryptogr. Eng., 2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
IACR Cryptol. ePrint Arch., 2014
Side-channel attack resistant AES cryptographic circuits with ROM reducing address-dependent EM leaks.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
A stable key generation from PUF responses with a Fuzzy Extractor for cryptographic authentications.
Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013
2012
High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications.
IEICE Trans. Electron., 2012
Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with Delay-Time Measurement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL.
Proceedings of the HOST 2011, 2011
2007
12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
IEICE Electron. Express, 2006
2005
A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip for Real-Time Robot Control with Multiprocessors.
J. Robotics Mechatronics, 2005
A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique.
IEICE Trans. Electron., 2005