Mitsuru Hiraki

According to our database, Mitsuru Hiraki authored at least 14 papers between 1991 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2023

An On-Chip DC-DC Converter and Power Management System Achieving Zero Standby-to-Active Transition Time in MCU.

Toyohiro Shimogawa, Makoto Nonaka, Toma Ogata, Toshiki Kiryu, Yasuto Igarashi, Kosuke Yayama, Masahiro Kitamura, Hiromichi Ishikura, Mitsuru Hiraki, Masao Ito, Takashi Kono

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2021

A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems.

Fukashi Morishita, Norihito Kato, Satoshi Okubo, Takao Toi, Mitsuru Hiraki, Sugako Otani, Hideaki Abe, Yuji Shinohara, Hiroyuki Kondo

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020

A High-Precision Analog Front End Integrated in a 32bit Microcontroller for Industrial Sensing Applications.

Koji Yoichi, Sugako Otani, Kazutoshi Tsuda, Naoya Tokimoto, Hideki Kamegawa, Yoshihisa Satou, Shioto Tanaka, Hideki Otsu, Mitsuru Hiraki, Masao Ito, Mitsuya Fukazawa, Hiroyuki Kondo

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2018

A Capacitance-to-Digital Converter Integrated in a 32bit Microcontroller for 3D Gesture Sensing.

Mitsuru Hiraki, Sugako Otani, Masao Ito, Takuya Mizokami, Masahiro Araki, Hiroyuki Kondo

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2004

A low-power microcontroller having a 0.5-μA standby current on-chip regulator with dual-reference scheme.

Mitsuru Hiraki, Kenichi Fukui, Takayasu Ito

IEEE J. Solid State Circuits, 2004

2002

A 63-μW standby power microcontroller with on-chip hybrid regulator scheme.

Mitsuru Hiraki, Takayasu Ito, Atsushi Fujiwara, Taichi Ohashi, Tetsuro Hamano, Takaaki Noda

IEEE J. Solid State Circuits, 2002

1999

Pre-silicon parameter generation methodology using BSIM3 for device/circuit concurrent design.

Mikako Miyama, Shiro Kamohara, Mitsuru Hiraki, Kazunori Onozawa, Hisaaki Kunitomo

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1997

Instruction buffering to reduce power in processors for signal processing.

Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki

IEEE Trans. Very Large Scale Integr. Syst., 1997

1996

Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer.

Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995

Data-dependent logic swing internal bus architecture for ultralow-power LSI's.

Mitsuru Hiraki, Hirotsugu Kojima, Hitoshi Misawa, Takashi Akazawa, Yuji Hatano

IEEE J. Solid State Circuits, April, 1995

1992

A 1.5-V full-swing BiCMOS logic circuit.

Mitsuru Hiraki, Kazuo Yano, Masataka Minami, Kazushige Sato, Nozomu Matsuzaki, Atsuo Watanabe, Takashi Nishida, Katsuro Sasaki, Koichi Seki

IEEE J. Solid State Circuits, November, 1992

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules.

Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, M. Hanawa, Masato Suzuki, S. Morita, A. Kawamata, Nagatoshi Ohki, Takashi Nishida, Koichi Seki

IEEE J. Solid State Circuits, March, 1992

1991

Quasi-complementary BiCMOS for sub-3-V digital circuits.

Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Yasuo Onose, Mitsuru Hirao, Nagatoshi Ohki, Takashi Nishida, Koichi Seki, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, November, 1991

On-Chip Multiple Superscalar Processors with Secondary Cache Memories.

M. Hanawa, Tadahiko Nishimukai, O. Nishii, Masato Suzuki, Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Takashi Nishida

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991