Mitsumasa Koyanagi
Orcid: 0000-0003-4726-4217
According to our database1,
Mitsumasa Koyanagi
authored at least 67 papers
between 1990 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1997, "For the invention of the stacked capacitor DRAM cell.".
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Impact of Super-long-throw PVD on TSV Metallization and Die-to-Wafer 3D Integration Based on Via-last.
Proceedings of the IEEE International 3D Systems Integration Conference, 2023
Proceedings of the IEEE International 3D Systems Integration Conference, 2023
2021
Proceedings of the IEEE International 3D Systems Integration Conference, 2021
Proceedings of the IEEE International 3D Systems Integration Conference, 2021
Implementation of a Chaotic Neural Network Reservoir on a TSV/μBump Stacked 3D Cyclic Neural Network Integrated Circuit.
Proceedings of the IEEE International 3D Systems Integration Conference, 2021
Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing.
Proceedings of the IEEE International 3D Systems Integration Conference, 2021
2020
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020
2019
Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-Integration.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
2016
Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration.
Micromachines, 2016
Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
3 Dimensional stacked pixel detector and sensor technology using less than 3-μmφ robust bump junctions.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
2015
Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
2013
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensor.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
Development of via-last 3D integration technologies using a new temporary adhesive system.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
A 19nm 112.8mm<sup>2</sup> 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration.
Micromachines, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integration.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
High-bandwidth data transmission of new transceiver module through optical interconnection.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSI.
Proceedings of the IEEE International Conference on 3D System Integration, 2010
Proceedings of the IEEE International Conference on 3D System Integration, 2010
A block-parallel signal processing system for CMOS image sensor with three-dimensional structure.
Proceedings of the IEEE International Conference on 3D System Integration, 2010
Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature.
Proceedings of the IEEE International Conference on 3D System Integration, 2010
2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the IEEE International Conference on 3D System Integration, 2009
Proceedings of the IEEE International Conference on 3D System Integration, 2009
Proceedings of the IEEE International Conference on 3D System Integration, 2009
Proceedings of the IEEE International Conference on 3D System Integration, 2009
Development of a new self-assembled die bonder to three-dimensionally stack known good dies in batch.
Proceedings of the IEEE International Conference on 3D System Integration, 2009
Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration.
Proceedings of the IEEE International Conference on 3D System Integration, 2009
2006
Proceedings of the 2006 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2006
2005
Dynamic Multi-Context Reconfiguration Scheme for Reconfigurable Parallel Image Processing System with Three Dimensional Structure.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005
2004
Design and Evaluation of a Novel Real-Shared Cache Module for High Performance Parallel Processor Chip.
Proceedings of the Parallel and Distributed Computing: Applications and Technologies, 2004
Design of A Novel Real-Shared Memory Module for High Performance Parallel Processor System with Shared Memory.
Proceedings of the 18th International Conference on Advanced Information Networking and Applications (AINA 2004), 2004
2003
Parallel image processing field programmable gate array for real time image processing system.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
2002
Proceedings of the 39th Design Automation Conference, 2002
2000
Proceedings of the Advances in Neural Information Processing Systems 13, 2000
1998
A New Multiport Memory for High Performance Parallel Processor System with Shared Memory.
Proceedings of the ASP-DAC '98, 1998
1991
A New Chip Architecture for VLSIs - Optical Coupled 3D Common Memory and Optical Interconnections.
Proceedings of the VLSI 91, 1991
1990
Design of 4-kbit*4-layer optically coupled three-dimensional common memory for parallel processor system.
IEEE J. Solid State Circuits, February, 1990