Mitsuko Saito

According to our database, Mitsuko Saito authored at least 9 papers between 2009 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×.

Noriyuki Miura, Mitsuko Saito, Masao Taguchi, Tadahiro Kuroda

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A 1 TB/s 1 pJ/b 6.4 mm²/(TB/s) QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM.

Noriyuki Miura, Mitsuko Saito, Tadahiro Kuroda

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

2011

A 2.7Gb/s/mm² 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking.

Noriyuki Miura, Yasuhiro Take, Mitsuko Saito, Yoichi Yoshida, Tadahiro Kuroda

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking.

Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking.

Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda

IEEE J. Solid State Circuits, 2010

A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking.

Mitsuko Saito, Noriyuki Miura, Tadahiro Kuroda

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

An 8Tb/s 1pJ/b 0.8mm²/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM.

Noriyuki Miura, Kazutaka Kasuga, Mitsuko Saito, Tadahiro Kuroda

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking.

Yasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking.

Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009