Mitsuhiro Togo

According to our database, Mitsuhiro Togo authored at least 5 papers between 1996 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements.

Felice Crupi, Massimo Alioto, Jacopo Franco, Paolo Magnone, Mitsuhiro Togo, N. Horiguchi, Guido Groeseneken

IEEE Trans. Circuits Syst. II Express Briefs, 2012

Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs.

Tommaso Romeo, Luigi Pantisano, Eddy Simoen, Raymond Krom, Mitsuhiro Togo, N. Horiguchi, Jérôme Mitard, Aaron Thean, Guido Groeseneken, Cor Claeys, Felice Crupi

Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2011

Positive bias temperature instabilities on sub-nanometer EOT FinFETs.

P. C. Feijoo, Moonju Cho, Mitsuhiro Togo, E. San Andrés, Guido Groeseneken

Microelectron. Reliab., 2011

2005

Device technology for body biasing scheme.

Kiyotaka Imai, Yasushi Yamagata, Sadaaki Masuoka, Naohiko Kimuzuka, Yuri Yasuda, Mitsuhiro Togo, Masahiro Ikeda, Yasutaka Nakashiba

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

1996

2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8: 1 multiplexers with a 0.15-μm CMOS technology.

Masakazu Kurisu, Makoto Kaneko, Tetsuyuki Suzaki, Akira Tanabe, Mitsuhiro Togo, Akio Furukawa, Takao Tamura, Ken Nakajima, Kazuyoshi Yoshida

IEEE J. Solid State Circuits, 1996