Mitsuhiro Hamada

According to our database, Mitsuhiro Hamada authored at least 5 papers between 1984 and 2000.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2000

A built-in self-repair analyzer (CRESTA) for embedded DRAMs.

Tomoya Kawagoe, Jun Ohtani, Mitsutaka Niiro, Tukasa Ooishi, Mitsuhiro Hamada, Hideto Hidaka

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1996

A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM.

Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1989

A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode.

Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima

IEEE J. Solid State Circuits, February, 1989

1986

Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode.

Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima, Y. Hayasaka

Proceedings of the Proceedings International Test Conference 1986, 1986

1984

A New Timing Calibration Method for High Speed Memory Test.

Yasumasa Nishimura, Mitsuhiro Hamada, Y. Hayasaka

Proceedings of the Proceedings International Test Conference 1984, 1984