Mitsuharu Nakazawa

According to our database, Mitsuharu Nakazawa authored at least 3 papers between 2002 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar Technology.

Shoichiro Kawashima, Keizo Morita, Mitsuharu Nakazawa, Kazuaki Yamane, Mitsuhiro Ogai, Kuninori Kawabata, Kazuaki Takai, Yasuhiro Fujii, Ryoji Yasuda, Wensheng Wang, Yukinobu Hikosaka, Ken'ichi Inoue

IEICE Trans. Electron., 2015

2007

A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip.

Shoichiro Kawashima, Isao Fukushi, Keizo Morita, Ken-ichi Nakabayashi, Mitsuharu Nakazawa, Kazuaki Yamane, Tomohisa Hirayama, Toru Endo

IEICE Trans. Electron., 2007

2002

Bitline GND sensing technique for low-voltage operation FeRAM.

Shoichiro Kawashima, Toru Endo, Akira Yamamoto, Ken-ichi Nakabayashi, Mitsuharu Nakazawa, Keizo Morita, Masaki Aoki

IEEE J. Solid State Circuits, 2002