Mititada Morisue

According to our database1, Mititada Morisue authored at least 15 papers between 1992 and 2003.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2003
Piecewise Linear Operators on Sigma-Delta Modulated Signals and Their Application.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Binary and multi-valued cellular array models of linear distributed parameter systems.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
Design of a multiple-operand redundant binary adder.
Syst. Comput. Jpn., 2002

Associative Memories Using Interaction between Multilayer Perceptrons and Sparsely Interconnected Neural Networks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Bit-Stream Signal Processing Circuits and Their Application.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Piecewise linear operations on sigma-delta modulated signals.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001
Method of Visualizing Homepages Using Certain Quantifiers and Its Verification.
Proceedings of the 15th International Conference on Information Networking, 2001

Dynamical intelligent network based on group representation theory.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
Shopping-chances in Web-pages discovered from user's access logs.
Proceedings of the Fourth International Conference on Knowledge-Based Intelligent Information Engineering Systems & Allied Technologies, 2000

Backpropagation Algorithm for Logic Oriented Neural Networks.
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000

1999
Arithmetic circuits for single-bit digital signal processing.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
Multiple-Valued Logic Oriented Neural Networks.
Proceedings of the International ICSC / IFAC Symposium on Neural Computation (NC 1998), 1998

A Josephson Ternary Memory Circuit.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

1997
A digital application of chaotic oscillation modes in Josephson circuit.
Int. J. Intell. Syst., 1997

1992
A Superconducting Ternary Systolic Array Processor.
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992


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