Mitchelle Rasquinha

According to our database, Mitchelle Rasquinha authored at least 6 papers between 2009 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A Metric Driven Approach to Mixed Precision Training.

Mitchelle Rasquinha, Gil Tabak

CoRR, 2024

2014

Manifold: A parallel simulation framework for multicore systems.

Jun Wang, Jesse G. Beu, Rishiraj A. Bheda, Tom Conte, Zhenjiang Dong, Chad D. Kersey, Mitchelle Rasquinha, George F. Riley, William J. Song, He Xiao, Peng Xu, Sudhakar Yalamanchili

Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

2011

A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective.

Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay

IEEE Trans. Very Large Scale Integr. Syst., 2011

Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments.

Syed Minhaj Hassan, Dhruv Choudhary, Mitchelle Rasquinha, Sudhakar Yalamanchili

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010

An energy efficient cache design using spin torque transfer (STT) RAM.

Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2009

A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies.

Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009